The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kami mencadangkan litar Jam dan Pemulihan Data (CDR) baharu untuk aplikasi mod pecah. Ia boleh memulihkan isyarat jam selepas dua peralihan data dan menahan urutan panjang digit yang sama berturut-turut. Dua Penjajaran Fasa Digital (DPA), yang dicetuskan oleh peningkatan atau penurunan tepi data input, memulihkan isyarat jam, yang kemudiannya digabungkan oleh interpolator fasa. Konfigurasi ini mengurangkan kegelisahan RMS jam pulih sebanyak 30% dan menggandakan panjang larian maksimum berbanding CDR DPA yang dilaporkan sebelum ini. Cip prototaip ditunjukkan dengan teknologi CMOS 0.18-µm. Keputusan pengukuran menunjukkan bahawa cip beroperasi tanpa sebarang ralat bit untuk 1.25-Gb/s 231-1 PRBS dengan frekuensi 200-ppm mengimbangi dan memulihkan jam dan data selepas dua kitaran jam.
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Salinan
Chang-Kyung SEONG, Seung-Woo LEE, Woo-Young CHOI, "A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator" in IEICE TRANSACTIONS on Communications,
vol. E91-B, no. 5, pp. 1397-1402, May 2008, doi: 10.1093/ietcom/e91-b.5.1397.
Abstract: We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.
URL: https://global.ieice.org/en_transactions/communications/10.1093/ietcom/e91-b.5.1397/_p
Salinan
@ARTICLE{e91-b_5_1397,
author={Chang-Kyung SEONG, Seung-Woo LEE, Woo-Young CHOI, },
journal={IEICE TRANSACTIONS on Communications},
title={A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator},
year={2008},
volume={E91-B},
number={5},
pages={1397-1402},
abstract={We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.},
keywords={},
doi={10.1093/ietcom/e91-b.5.1397},
ISSN={1745-1345},
month={May},}
Salinan
TY - JOUR
TI - A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator
T2 - IEICE TRANSACTIONS on Communications
SP - 1397
EP - 1402
AU - Chang-Kyung SEONG
AU - Seung-Woo LEE
AU - Woo-Young CHOI
PY - 2008
DO - 10.1093/ietcom/e91-b.5.1397
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E91-B
IS - 5
JA - IEICE TRANSACTIONS on Communications
Y1 - May 2008
AB - We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.
ER -