The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Suis dan penghala berkelajuan tinggi pada masa hadapan dijangka menyokong sejumlah besar port pada kadar talian tinggi yang membawa trafik dengan sifat statistik yang pelbagai. Sehubungan itu, mekanisme penjadualan diperlukan untuk mengendalikan kapasiti agregat Tbit/saat sambil menyediakan jaminan kualiti perkhidmatan (QoS). Dalam makalah ini, skim pensuisan kapasiti tinggi baru untuk rangkaian ATM/WDM dibentangkan. Seni bina yang dicadangkan adalah bebas perbalahan, berskala, mudah dilaksanakan dan tidak memerlukan "percepatan" dalaman. Pengedaran destinasi yang tidak seragam dan ketibaan sel pecah diperiksa semasa mengkaji prestasi pensuisan. Keputusan simulasi menunjukkan bahawa pada daya pemprosesan agregat 1 Tbit/saat, kependaman rendah dicapai, menghasilkan penyelesaian yang berkuasa untuk rangkaian suis paket berprestasi tinggi.
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Salinan
Itamar ELHANANY, Dan SADOT, "A Contention-Free Tbit/sec Packet-Switching Architecture for ATM over WDM Networks" in IEICE TRANSACTIONS on Communications,
vol. E83-B, no. 2, pp. 225-230, February 2000, doi: .
Abstract: Future high-speed switches and routers will be expected to support a large number of ports at high line rates carrying traffic with diverse statistical properties. Accordingly, scheduling mechanisms will be required to handle Tbit/sec aggregated capacity while providing quality of service (QoS) guarantees. In this paper a novel high-capacity switching scheme for ATM/WDM networks is presented. The proposed architecture is contention-free, scalable, easy to implement and requires no internal "speedup. " Non-uniform destination distribution and bursty cell arrivals are examined when studying the switching performance. Simulation results show that at an aggregated throughput of 1 Tbit/sec, low latency is achieved, yielding a powerful solution for high-performance packet-switch networks.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e83-b_2_225/_p
Salinan
@ARTICLE{e83-b_2_225,
author={Itamar ELHANANY, Dan SADOT, },
journal={IEICE TRANSACTIONS on Communications},
title={A Contention-Free Tbit/sec Packet-Switching Architecture for ATM over WDM Networks},
year={2000},
volume={E83-B},
number={2},
pages={225-230},
abstract={Future high-speed switches and routers will be expected to support a large number of ports at high line rates carrying traffic with diverse statistical properties. Accordingly, scheduling mechanisms will be required to handle Tbit/sec aggregated capacity while providing quality of service (QoS) guarantees. In this paper a novel high-capacity switching scheme for ATM/WDM networks is presented. The proposed architecture is contention-free, scalable, easy to implement and requires no internal "speedup. " Non-uniform destination distribution and bursty cell arrivals are examined when studying the switching performance. Simulation results show that at an aggregated throughput of 1 Tbit/sec, low latency is achieved, yielding a powerful solution for high-performance packet-switch networks.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - A Contention-Free Tbit/sec Packet-Switching Architecture for ATM over WDM Networks
T2 - IEICE TRANSACTIONS on Communications
SP - 225
EP - 230
AU - Itamar ELHANANY
AU - Dan SADOT
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E83-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2000
AB - Future high-speed switches and routers will be expected to support a large number of ports at high line rates carrying traffic with diverse statistical properties. Accordingly, scheduling mechanisms will be required to handle Tbit/sec aggregated capacity while providing quality of service (QoS) guarantees. In this paper a novel high-capacity switching scheme for ATM/WDM networks is presented. The proposed architecture is contention-free, scalable, easy to implement and requires no internal "speedup. " Non-uniform destination distribution and bursty cell arrivals are examined when studying the switching performance. Simulation results show that at an aggregated throughput of 1 Tbit/sec, low latency is achieved, yielding a powerful solution for high-performance packet-switch networks.
ER -