The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Beberapa kaedah pelaksanaan untuk a Penyahkod MAP dicadangkan dalam kertas kerja ini. Menggunakan novel proses perkongsian masa berstruktur saluran paip, pengarang dapat mengatasi sekatan yang dikenakan oleh proses rekursi pada metrik keadaan dengan cekap, dan kerumitan Penyahkod MAP boleh dikurangkan ke tahap mengikut susunan a Penyahkod SOVA (Soft Output Viterbi Algorithm).. Di samping itu, penulis mencadangkan struktur pengawal yang cekap yang boleh digunakan untuk sistem saiz bingkai berubah-ubah seperti cdma-2000. The Penyahkod MAP menggunakan a dari segi blok algoritma yang direka di sini telah dilaksanakan hanya dalam satu litar 20,000 get. Ia telah disahkan oleh VHDL, yang dibandingkan dengan keputusan simulasi awal (program C). Penyahkod menunjukkan keupayaan pemprosesan penyahkodan 300 kbps dengan 8 lelaran pada litar FPGA, dengan sisihan hanya kira-kira 0.1-0.2 dB lebih besar daripada itu untuk penyahkod MAP yang ideal, walaupun apabila semua persekitaran perkakasan dipertimbangkan.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Goo-Hyun PARK, Suk-Hyon YOON, Daesik HONG, Chang-Eon KANG, "Design for a Turbo-Code Decoder Using a Block-Wise Algorithm" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 2, pp. 559-564, February 2002, doi: .
Abstract: Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_2_559/_p
Salinan
@ARTICLE{e85-b_2_559,
author={Goo-Hyun PARK, Suk-Hyon YOON, Daesik HONG, Chang-Eon KANG, },
journal={IEICE TRANSACTIONS on Communications},
title={Design for a Turbo-Code Decoder Using a Block-Wise Algorithm},
year={2002},
volume={E85-B},
number={2},
pages={559-564},
abstract={Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - Design for a Turbo-Code Decoder Using a Block-Wise Algorithm
T2 - IEICE TRANSACTIONS on Communications
SP - 559
EP - 564
AU - Goo-Hyun PARK
AU - Suk-Hyon YOON
AU - Daesik HONG
AU - Chang-Eon KANG
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2002
AB - Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.
ER -