The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Satu gelung terkunci fasa terkunci cepat (DCPLL) dikawal secara digital dicadangkan dalam surat ini. DCPLL ini menggunakan algoritma carian kekerapan baru untuk mengurangkan masa kunci masuk. Tambahan pula, untuk mengurangkan penggunaan kuasa, pembahagi frekuensi digunakan semula sebagai pengesan frekuensi semasa pemerolehan frekuensi, dan digunakan semula sebagai modul penukar masa-ke-digital semasa pemerolehan fasa. Untuk mengesahkan algoritma dan seni bina yang dicadangkan, reka bentuk DCPLL dilaksanakan oleh teknologi SMIC 0.18 µm 1P6M CMOS. Keputusan simulasi Spice menunjukkan bahawa DCPLL boleh mencapai pemerolehan frekuensi dalam 3 kitaran rujukan dan pemerolehan fasa lengkap dalam 11 kitaran rujukan apabila mengunci kepada 200 MHz. Penggunaan kuasa DCPLL yang sepadan ialah 3.71 mW.
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Salinan
Xin CHEN, Jun YANG, Long-xing SHI, "A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 12, pp. 1971-1975, December 2008, doi: 10.1093/ietele/e91-c.12.1971.
Abstract: A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.12.1971/_p
Salinan
@ARTICLE{e91-c_12_1971,
author={Xin CHEN, Jun YANG, Long-xing SHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop},
year={2008},
volume={E91-C},
number={12},
pages={1971-1975},
abstract={A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.},
keywords={},
doi={10.1093/ietele/e91-c.12.1971},
ISSN={1745-1353},
month={December},}
Salinan
TY - JOUR
TI - A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop
T2 - IEICE TRANSACTIONS on Electronics
SP - 1971
EP - 1975
AU - Xin CHEN
AU - Jun YANG
AU - Long-xing SHI
PY - 2008
DO - 10.1093/ietele/e91-c.12.1971
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2008
AB - A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.
ER -