The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kesan gangguan elektromagnet (EM) (kekebalan) terhadap pengendalian litar LSI dalam persekitaran berpakej QFP dan dipasang PCB dikaji. Suntikan kuasa EM ke sistem bekalan kuasa membawa kepada pincang fungsi, di mana kuasa diterjemahkan kepada lantunan voltan melalui gabungan galangan on- dan off-cip, yang menjejaskan bekalan kuasa dan pembumian, serta nod isyarat dalam dadu, dilihat dari on- ukuran bentuk gelombang cip. Model impedans bekalan kuasa terkumpul dan amplitud minimum lantunan voltan yang disebabkan oleh kuasa EM untuk kerosakan, kedua-duanya boleh diperoleh daripada pengukuran luaran kepada LSI berpakej tertentu, merumuskan model gangguan EM yang membantu dalam reka bentuk PCB ke arah tinggi. imuniti. Teknik ini secara amnya boleh digunakan untuk aplikasi sistem pada cip.
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Salinan
Kouji ICHIKAWA, Yuki TAKAHASHI, Yukihiko SAKURAI, Takahiro TSUDA, Isao IWASE, Makoto NAGATA, "Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 6, pp. 936-944, June 2008, doi: 10.1093/ietele/e91-c.6.936.
Abstract: Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.6.936/_p
Salinan
@ARTICLE{e91-c_6_936,
author={Kouji ICHIKAWA, Yuki TAKAHASHI, Yukihiko SAKURAI, Takahiro TSUDA, Isao IWASE, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation},
year={2008},
volume={E91-C},
number={6},
pages={936-944},
abstract={Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.},
keywords={},
doi={10.1093/ietele/e91-c.6.936},
ISSN={1745-1353},
month={June},}
Salinan
TY - JOUR
TI - Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 936
EP - 944
AU - Kouji ICHIKAWA
AU - Yuki TAKAHASHI
AU - Yukihiko SAKURAI
AU - Takahiro TSUDA
AU - Isao IWASE
AU - Makoto NAGATA
PY - 2008
DO - 10.1093/ietele/e91-c.6.936
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2008
AB - Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.
ER -