The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Surat ini membentangkan op-amp voltan rendah 0.5 V dalam proses CMOS standard 0.18 µm untuk litar kapasitor tersuis. Tidak seperti seni bina op-amp 0.5 V dua peringkat lain, op-amp ini terdiri daripada penyongsang CMOS yang menggunakan sumber voltan terapung dan pincang badan ke hadapan untuk mendapatkan operasi berkelajuan tinggi. Dan dua litar penolakan mod biasa yang dipertingkatkan digabungkan dengan baik untuk mencapai pengurangan kuasa rendah dan kawasan cip. Keputusan simulasi menunjukkan bahawa op-amp mempunyai keuntungan gelung terbuka sebanyak 62 dB, dan lebar jalur keuntungan perpaduan yang tinggi sebanyak 56 MHz. Penggunaan kuasa hanya 350 µW.
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Salinan
Jun WANG, Tuck-Yang LEE, Dong-Gyou KIM, Toshimasa MATSUOKA, Kenji TANIGUCHI, "Design of a 0.5 V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 8, pp. 1375-1378, August 2008, doi: 10.1093/ietele/e91-c.8.1375.
Abstract: This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.8.1375/_p
Salinan
@ARTICLE{e91-c_8_1375,
author={Jun WANG, Tuck-Yang LEE, Dong-Gyou KIM, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a 0.5 V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources},
year={2008},
volume={E91-C},
number={8},
pages={1375-1378},
abstract={This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.},
keywords={},
doi={10.1093/ietele/e91-c.8.1375},
ISSN={1745-1353},
month={August},}
Salinan
TY - JOUR
TI - Design of a 0.5 V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources
T2 - IEICE TRANSACTIONS on Electronics
SP - 1375
EP - 1378
AU - Jun WANG
AU - Tuck-Yang LEE
AU - Dong-Gyou KIM
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2008
DO - 10.1093/ietele/e91-c.8.1375
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2008
AB - This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.
ER -