The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dua pengesan fasa (PD) dicadangkan untuk meminimumkan offset fasa dan zon mati apabila digunakan dalam DLL atau PLL. Dengan laluan perlumbaan simetri terpendek dari kedua-dua input, PD binari mencapai operasi selak pantas dan penyingkiran teori masa persediaan. Berbeza dengan PD konvensional yang offsetnya adalah sekitar 10 ps dengan kepekaan yang besar terhadap saiz, PD binari yang dicadangkan menunjukkan offset kurang daripada 1 ps dengan pengurangan masa tunda 30 peratus. Pengesanan fasa binari jenis selak yang dicadangkan juga diperluaskan untuk membentuk PD linear dengan penambahan litar penjanaan semula.
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Salinan
Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon SIM, "Deadzone-Minimized Systematic Offset-Free Phase Detectors" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1525-1528, September 2008, doi: 10.1093/ietele/e91-c.9.1525.
Abstract: Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1525/_p
Salinan
@ARTICLE{e91-c_9_1525,
author={Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon SIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Deadzone-Minimized Systematic Offset-Free Phase Detectors},
year={2008},
volume={E91-C},
number={9},
pages={1525-1528},
abstract={Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.},
keywords={},
doi={10.1093/ietele/e91-c.9.1525},
ISSN={1745-1353},
month={September},}
Salinan
TY - JOUR
TI - Deadzone-Minimized Systematic Offset-Free Phase Detectors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1525
EP - 1528
AU - Young-Sang KIM
AU - Yunjae SUH
AU - Hong-June PARK
AU - Jae-Yoon SIM
PY - 2008
DO - 10.1093/ietele/e91-c.9.1525
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.
ER -