The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Penggunaan kuasa ultra-rendah dan litar DCFL berkelajuan tinggi telah direka dengan menggunakan 0.2-µm gerbang berbentuk Y E/D-heterojunction-FET (HJFET) dengan struktur get nisbah aspek tinggi, yang mempunyai kelebihan. mengurangkan kapasitans pinggir pintu (Cf) kepada kira-kira separuh daripada nisbah aspek rendah konvensional. Pengayun gelang 51 peringkat fabrikasi dengan gerbang berbentuk Y 0.2-µm n-AlGaAs/i-InGaAs E/D-HJFETs menunjukkan produk tunda kuasa terendah 0.21 fJ dengan kelewatan perambatan tidak dimuatkan sebanyak 34.9 ps pada voltan bekalan (VDD) sebanyak 0.4 V. Kami juga menganalisis ciri pensuisan DCFL dengan mengambil kira kapasitans get-ke-sumber intrinsik (Cgsint) Dan Cf. Keputusan analisis untuk produk kelewatan kuasa bersetuju dengan keputusan percubaan kami. Analisis kami juga menunjukkan litar DCFL dengan nisbah aspek tinggi gerbang berbentuk Y E/D-HJFET boleh mengurangkan produk kelewatan kuasa sebanyak 35% atau lebih di bawah 0.25-µm panjang pintu berbanding dengan yang konvensional dengan rendah. -Nisbah aspek HJFET gerbang berbentuk Y. Keputusan ini menjelaskan bahawa Cf-pengurangan HJFET get berbentuk Y adalah lebih berkesan dalam meningkatkan produk kelewatan kuasa daripada mengurangkan panjang get.
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Salinan
Shigeki WADA, Masatoshi TOKUSHIMA, Masaoki ISHIKAWA, Nobuhide YOSHIDA, Masahiro FUJII, Tadashi MAEDA, "0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 3, pp. 491-497, March 1999, doi: .
Abstract: Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_3_491/_p
Salinan
@ARTICLE{e82-c_3_491,
author={Shigeki WADA, Masatoshi TOKUSHIMA, Masaoki ISHIKAWA, Nobuhide YOSHIDA, Masahiro FUJII, Tadashi MAEDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs},
year={1999},
volume={E82-C},
number={3},
pages={491-497},
abstract={Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.},
keywords={},
doi={},
ISSN={},
month={March},}
Salinan
TY - JOUR
TI - 0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 491
EP - 497
AU - Shigeki WADA
AU - Masatoshi TOKUSHIMA
AU - Masaoki ISHIKAWA
AU - Nobuhide YOSHIDA
AU - Masahiro FUJII
AU - Tadashi MAEDA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1999
AB - Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.
ER -