The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kaedah pencirian lanjutan untuk transistor sel DRAM sub-mikron telah dicadangkan untuk analisis struktur ujian transistor menggunakan corak sel memori. Apabila susun atur sel memori sebenar digunakan sebagai struktur ujian, sumber parasit dan rintangan saliran struktur ujian menjejaskan parameter transistor konvensional seperti voltan ambang. Untuk menyelesaikan masalah ini, kaedah pengukuran arus longkang yang dikurangkan telah dicadangkan untuk menyekat penurunan voltan rintangan parasit. Dalam pengukuran ini, dua parameter transistor baharu, Vgoff and Vgsat, telah dicadangkan yang berkaitan dengan kebocoran luar dan penulisan penuh, masing-masing. Parameter ini didapati sebagai parameter yang baik untuk memantau kegagalan bit DRAM. Metodologi pengukuran voltan ambang baharu juga telah dicadangkan untuk struktur ujian dengan rintangan parasit yang tinggi.
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Salinan
Ikuo KURACHI, "Advanced Characterization Method for Sub-Micron DRAM Cell Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 4, pp. 618-623, April 1999, doi: .
Abstract: An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, Vgoff and Vgsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_4_618/_p
Salinan
@ARTICLE{e82-c_4_618,
author={Ikuo KURACHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Advanced Characterization Method for Sub-Micron DRAM Cell Transistors},
year={1999},
volume={E82-C},
number={4},
pages={618-623},
abstract={An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, Vgoff and Vgsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.},
keywords={},
doi={},
ISSN={},
month={April},}
Salinan
TY - JOUR
TI - Advanced Characterization Method for Sub-Micron DRAM Cell Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 618
EP - 623
AU - Ikuo KURACHI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1999
AB - An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, Vgoff and Vgsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.
ER -