The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kesan perubahan saiz lot dan logistik pemprosesan ujian ke atas kecekapan proses ujian akhir pembuatan VLSI dan kos disebabkan oleh peralihan daripada saiz wafer daripada 5 atau 6 inci konvensional kepada 300 mm (12 inci) dinilai melalui analisis simulasi. Keputusan simulasi menunjukkan kecekapan ujian yang tinggi dan kos ujian yang rendah dikekalkan tanpa mengira saiz lot ketibaan dalam julat bilangan wafer 300 mm setiap lot dari 1 hingga 25 dan kandungan lot ekspres dalam julat sehingga 50% dengan menggunakan peraturan BERAT+RPM dan logistik pemprosesan ujian akhir yang betul. Peraturan WEIGHT+RPM ialah peraturan yang mempertimbangkan masa pertukaran jig dan suhu, masa menunggu lot dalam baris gilir dan juga baki masa pemprosesan mesin yang digunakan. Logistik mempunyai pemprosesan kecil dan saiz lot bergerak sama dengan saiz kelompok peralatan ujian.
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Salinan
Akihisa CHIKAMURA, Koji NAKAMAE, Hiromu FUJIOKA, "Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 4, pp. 638-645, April 1999, doi: .
Abstract: The effect of lot size change and test processing logistics on VLSI manufacturing final test process efficiency and cost due to the transition of from conventional 5 or 6 inches to 300 mm (12 inches) in wafer size is evaluated through simulation analysis. Simulated results show that a high test efficiency and a low test cost are maintained regardless of arrival lot size in the range of the number of 300 mm wafers per lot from 1 to 25 and the content of express lots in the range of up to 50% by using WEIGHT+RPM rule and the right final test processing logistics. WEIGHT+RPM rule is the rule that considers the jig and temperature exchanging time, the lot waiting time in queue and also the remaining processing time of the machine in use. The logistics has a small processing and moving lot size equal to the batch size of testing equipment.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_4_638/_p
Salinan
@ARTICLE{e82-c_4_638,
author={Akihisa CHIKAMURA, Koji NAKAMAE, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost},
year={1999},
volume={E82-C},
number={4},
pages={638-645},
abstract={The effect of lot size change and test processing logistics on VLSI manufacturing final test process efficiency and cost due to the transition of from conventional 5 or 6 inches to 300 mm (12 inches) in wafer size is evaluated through simulation analysis. Simulated results show that a high test efficiency and a low test cost are maintained regardless of arrival lot size in the range of the number of 300 mm wafers per lot from 1 to 25 and the content of express lots in the range of up to 50% by using WEIGHT+RPM rule and the right final test processing logistics. WEIGHT+RPM rule is the rule that considers the jig and temperature exchanging time, the lot waiting time in queue and also the remaining processing time of the machine in use. The logistics has a small processing and moving lot size equal to the batch size of testing equipment.},
keywords={},
doi={},
ISSN={},
month={April},}
Salinan
TY - JOUR
TI - Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
T2 - IEICE TRANSACTIONS on Electronics
SP - 638
EP - 645
AU - Akihisa CHIKAMURA
AU - Koji NAKAMAE
AU - Hiromu FUJIOKA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1999
AB - The effect of lot size change and test processing logistics on VLSI manufacturing final test process efficiency and cost due to the transition of from conventional 5 or 6 inches to 300 mm (12 inches) in wafer size is evaluated through simulation analysis. Simulated results show that a high test efficiency and a low test cost are maintained regardless of arrival lot size in the range of the number of 300 mm wafers per lot from 1 to 25 and the content of express lots in the range of up to 50% by using WEIGHT+RPM rule and the right final test processing logistics. WEIGHT+RPM rule is the rule that considers the jig and temperature exchanging time, the lot waiting time in queue and also the remaining processing time of the machine in use. The logistics has a small processing and moving lot size equal to the batch size of testing equipment.
ER -