The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Hierarki reka bentuk baharu dalam TCAD dibincangkan dengan penekanan pada reka bentuk sambungan IC dan corak get. Dua metodologi reka bentuk untuk corak get pada peringkat sel CMOS dan skema sambung berbilang peringkat pada tahap cip dicadangkan. Pendekatan ini menjana peraturan reka bentuk susun atur corak get, dengan mengambil kira proses fabrikasi dan pergantungan reka letak corak, dan membenarkan reka bentuk skema intersambung berbilang peringkat pada fasa awal pembangunan teknologi.
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Salinan
Shinji ODANAKA, Akio MISAKA, Kyoji YAMASHITA, "A Design Hierarchy of IC Interconnects and Gate Patterns" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 6, pp. 948-954, June 1999, doi: .
Abstract: A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_6_948/_p
Salinan
@ARTICLE{e82-c_6_948,
author={Shinji ODANAKA, Akio MISAKA, Kyoji YAMASHITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Design Hierarchy of IC Interconnects and Gate Patterns},
year={1999},
volume={E82-C},
number={6},
pages={948-954},
abstract={A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - A Design Hierarchy of IC Interconnects and Gate Patterns
T2 - IEICE TRANSACTIONS on Electronics
SP - 948
EP - 954
AU - Shinji ODANAKA
AU - Akio MISAKA
AU - Kyoji YAMASHITA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1999
AB - A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.
ER -