The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Metodologi penentuan parameter talian penghantaran intersambung IC baharu dan teknik simulasi pantas baharu untuk talian penghantaran tidak seragam dipersembahkan dan disahkan. Parameter kapasitansi adalah fungsi kuat kesan perisai antara lapisan, manakala substrat silikon mempunyai kesan yang besar pada parameter kearuhan. Oleh itu, mereka diambil kira untuk menentukan parameter. Kemudian parameter panjang berasaskan garis lurus maya bagi setiap unit ditentukan untuk melaksanakan simulasi sementara pantas bagi talian penghantaran tidak seragam. Telah ditunjukkan bahawa bukan sahaja kesan induktansi disebabkan oleh substrat silikon tetapi juga kesan perisai antara lapisan adalah terlalu ketara untuk diabaikan. Selanjutnya, teknik pengurangan pesanan model disepadukan ke dalam Berkeley SPICE untuk menunjukkan bahawa parameter panjang per unit berasaskan garis lurus maya boleh digunakan dengan cekap untuk simulasi tindak balas sementara pantas bagi struktur interkoneksi berbilang lapisan yang rumit. Memandangkan metodologi ini sangat cekap serta tepat, ia boleh digunakan secara berguna untuk alatan IC CAD bagi reka bentuk litar VLSI berprestasi tinggi.
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Salinan
Woojin JIN, Hanjong YOO, Yungseon EO, "Non-uniform Multi-Layer IC Interconnect Transmission Line Characterization for Fast Signal Transient Simulation of High-Speed/High-Density VLSI Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 6, pp. 955-966, June 1999, doi: .
Abstract: A new IC interconnect transmission line parameter determination methodology and a novel fast simulation technique for non-uniform transmission lines are presented and verified. The capacitance parameter is a strong function of a shielding effect between the layers, while silicon substrate has a substantial effect on inductance parameter. Thus, they are taken into account to determine the parameters. Then the virtual straight-line-based per unit length parameters are determined in order to perform the fast transient simulation of the non-uniform transmission lines. It was shown that not only the inductance effect due to a silicon substrate but also the shielding effect between the layers are too significant to be neglected. Further, a model order reduction technique is integrated into Berkeley SPICE in order to demonstrate that the virtual straight-line-based per-unit-length parameters can be efficiently employed for the fast transient response simulation of the complicated multi-layer interconnect structures. Since the methodology is very efficient as well as accurate, it can be usefully employed for IC CAD tools of high-performance VLSI circuit design.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_6_955/_p
Salinan
@ARTICLE{e82-c_6_955,
author={Woojin JIN, Hanjong YOO, Yungseon EO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Non-uniform Multi-Layer IC Interconnect Transmission Line Characterization for Fast Signal Transient Simulation of High-Speed/High-Density VLSI Circuits},
year={1999},
volume={E82-C},
number={6},
pages={955-966},
abstract={A new IC interconnect transmission line parameter determination methodology and a novel fast simulation technique for non-uniform transmission lines are presented and verified. The capacitance parameter is a strong function of a shielding effect between the layers, while silicon substrate has a substantial effect on inductance parameter. Thus, they are taken into account to determine the parameters. Then the virtual straight-line-based per unit length parameters are determined in order to perform the fast transient simulation of the non-uniform transmission lines. It was shown that not only the inductance effect due to a silicon substrate but also the shielding effect between the layers are too significant to be neglected. Further, a model order reduction technique is integrated into Berkeley SPICE in order to demonstrate that the virtual straight-line-based per-unit-length parameters can be efficiently employed for the fast transient response simulation of the complicated multi-layer interconnect structures. Since the methodology is very efficient as well as accurate, it can be usefully employed for IC CAD tools of high-performance VLSI circuit design.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - Non-uniform Multi-Layer IC Interconnect Transmission Line Characterization for Fast Signal Transient Simulation of High-Speed/High-Density VLSI Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 955
EP - 966
AU - Woojin JIN
AU - Hanjong YOO
AU - Yungseon EO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1999
AB - A new IC interconnect transmission line parameter determination methodology and a novel fast simulation technique for non-uniform transmission lines are presented and verified. The capacitance parameter is a strong function of a shielding effect between the layers, while silicon substrate has a substantial effect on inductance parameter. Thus, they are taken into account to determine the parameters. Then the virtual straight-line-based per unit length parameters are determined in order to perform the fast transient simulation of the non-uniform transmission lines. It was shown that not only the inductance effect due to a silicon substrate but also the shielding effect between the layers are too significant to be neglected. Further, a model order reduction technique is integrated into Berkeley SPICE in order to demonstrate that the virtual straight-line-based per-unit-length parameters can be efficiently employed for the fast transient response simulation of the complicated multi-layer interconnect structures. Since the methodology is very efficient as well as accurate, it can be usefully employed for IC CAD tools of high-performance VLSI circuit design.
ER -