The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Litar penyegerakan bit pemerolehan pantas novel 10-Gb/s untuk digunakan dalam suis paket optik throughput Tb/s telah dibangunkan. Litar ialah jenis pemilihan data sampel terbaik berdasarkan jam berbilang fasa, dan ia memproses paket input tak segerak ke dalam aliran data segerak secara bersiri, yang berfaedah dari segi skala litar dan kuasa penggunaan berbanding dengan jenis pemprosesan selari. Litar ini dibangunkan menggunakan tatasusunan get ultrahigh-speed Si-bipolar dan ia digunakan untuk membangunkan modul penerima paket tak segerak optik 10-Gb/s. Logik teras modul litar ini memerlukan kira-kira 100 pintu, menggunakan 6 W, dan saiz modul dikurangkan kepada hanya 170 mm (W)
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Salinan
Akio TAJIMA, Hiroaki TAKAHASHI, Yoshiharu MAENO, Soichiro ARAKI, Naoya HENMI, "A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 8, pp. 1387-1392, August 1999, doi: .
Abstract: A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_8_1387/_p
Salinan
@ARTICLE{e82-c_8_1387,
author={Akio TAJIMA, Hiroaki TAKAHASHI, Yoshiharu MAENO, Soichiro ARAKI, Naoya HENMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit},
year={1999},
volume={E82-C},
number={8},
pages={1387-1392},
abstract={A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
keywords={},
doi={},
ISSN={},
month={August},}
Salinan
TY - JOUR
TI - A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 1387
EP - 1392
AU - Akio TAJIMA
AU - Hiroaki TAKAHASHI
AU - Yoshiharu MAENO
AU - Soichiro ARAKI
AU - Naoya HENMI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1999
AB - A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)
ER -