The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Reka bentuk litar penguat deria berasaskan resonant-tunneling-diode (RTD) telah dicadangkan buat kali pertama untuk membayangkan sistem memori berkelajuan tinggi dan berkuasa rendah yang turut merangkumi sel memori berasaskan RTD padat tanpa penyegaran. Dengan menggabungkan RTD dengan transistor jenis-n bagi peranti semikonduktor oksida logam pelengkap konvensional (CMOS), keluarga litar logik kuantum MOS (Q-MOS) baharu, yang mempunyai produk kelewatan kuasa yang sangat rendah dan imuniti hingar yang baik, telah dibangunkan baru-baru ini. Kertas kerja ini memperkenalkan reka bentuk dan analisis litar penguat deria QMOS baharu, yang terdiri daripada sepasang RTD sebagai beban tarik naik bersama-sama dengan transistor tarik-turun jenis-n. Litar pengesan QMOS yang dicadangkan mempamerkan masa pengesanan hampir 20% lebih pantas berbanding reka bentuk konvensional penguat deria CMOS. Analisis kestabilan yang dilakukan menggunakan rajah plot fasa mendedahkan bahawa pasangan penyongsang QMOS statik bersambung belakang ke belakang, yang membentuk teras penguat deria, mempunyai keadaan meta-stabil dan tidak stabil yang berkait rapat dengan ciri IV bagi RTD. Makalah ini juga menganalisis secara terperinci reka bentuk sel memori tanpa segar semula, yang dikenali sebagai memori capaian rawak statik terowong (TSRAM). Reka bentuk sel yang inovatif menambah timbunan dua RTD pada sel RAM dinamik (DRAM) satu transistor konvensional dan dengan itu sel boleh menahan paras casnya selama-lamanya tanpa sebarang penyegaran berkala lagi. Analisis menunjukkan bahawa sel TSRAM boleh mencapai kira-kira dua susunan magnitud kuasa siap sedia lebih rendah daripada sel DRAM konvensional. Kertas kerja itu menunjukkan bahawa litar berasaskan RTD memegang janji yang tinggi dan berkemungkinan menjadi calon utama untuk sistem memori berketumpatan tinggi, berprestasi tinggi dan berkuasa rendah masa hadapan.
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Salinan
Tetsuya UEMURA, Pinaki MAZUMDER, "Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory System" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1630-1637, September 1999, doi: .
Abstract: A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a very high-speed and low-power memory system that also includes refresh-free, compact RTD-based memory cells. By combining RTDs with n-type transistors of conventional complementary metal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) family of logic circuits, having very low power-delay product and good noise immunity, has recently been developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly 20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stability analysis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable and unstable states which are closely related to the I-V characteristics of the RTDs. The paper also analyzes in details the refresh-free memory cell design, known as tunneling static random access memory (TSRAM). The innovative cell design adds a stack of two RTDs to the conventional one-transistor dynamic RAM (DRAM) cell and thereby the cell can indefinitely hold its charge level without any further periodic refreshing. The analysis indicates that the TSRAM cell can achieve about two orders of magnitude lower stand-by power than a conventional DRAM cell. The paper demonstrates that RTD-based circuits hold high promises and are likely to be the key candidates for the future high-density, high-performance and low-power memory systems.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1630/_p
Salinan
@ARTICLE{e82-c_9_1630,
author={Tetsuya UEMURA, Pinaki MAZUMDER, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory System},
year={1999},
volume={E82-C},
number={9},
pages={1630-1637},
abstract={A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a very high-speed and low-power memory system that also includes refresh-free, compact RTD-based memory cells. By combining RTDs with n-type transistors of conventional complementary metal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) family of logic circuits, having very low power-delay product and good noise immunity, has recently been developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly 20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stability analysis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable and unstable states which are closely related to the I-V characteristics of the RTDs. The paper also analyzes in details the refresh-free memory cell design, known as tunneling static random access memory (TSRAM). The innovative cell design adds a stack of two RTDs to the conventional one-transistor dynamic RAM (DRAM) cell and thereby the cell can indefinitely hold its charge level without any further periodic refreshing. The analysis indicates that the TSRAM cell can achieve about two orders of magnitude lower stand-by power than a conventional DRAM cell. The paper demonstrates that RTD-based circuits hold high promises and are likely to be the key candidates for the future high-density, high-performance and low-power memory systems.},
keywords={},
doi={},
ISSN={},
month={September},}
Salinan
TY - JOUR
TI - Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory System
T2 - IEICE TRANSACTIONS on Electronics
SP - 1630
EP - 1637
AU - Tetsuya UEMURA
AU - Pinaki MAZUMDER
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a very high-speed and low-power memory system that also includes refresh-free, compact RTD-based memory cells. By combining RTDs with n-type transistors of conventional complementary metal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) family of logic circuits, having very low power-delay product and good noise immunity, has recently been developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly 20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stability analysis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable and unstable states which are closely related to the I-V characteristics of the RTDs. The paper also analyzes in details the refresh-free memory cell design, known as tunneling static random access memory (TSRAM). The innovative cell design adds a stack of two RTDs to the conventional one-transistor dynamic RAM (DRAM) cell and thereby the cell can indefinitely hold its charge level without any further periodic refreshing. The analysis indicates that the TSRAM cell can achieve about two orders of magnitude lower stand-by power than a conventional DRAM cell. The paper demonstrates that RTD-based circuits hold high promises and are likely to be the key candidates for the future high-density, high-performance and low-power memory systems.
ER -