The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Seni bina VLSI logik-dalam-memori baharu berdasarkan logik transistor laluan terapung-gate-MOS berbilang nilai dicadangkan untuk menyelesaikan kesesakan komunikasi antara modul memori dan logik. Data tersimpan berbilang nilai diwakili oleh voltan ambang transistor MOS pintu terapung, supaya satu transistor MOS pintu terapung digunakan secara berkesan untuk menggabungkan fungsi ambang-huruf berbilang nilai dan suis pas. Sebagai aplikasi, VLSI logik-dalam-memori bernilai empat untuk pengecaman corak berkelajuan tinggi turut dipersembahkan. VLSI yang dicadangkan mengesan perkataan rujukan yang disimpan dengan jarak Manhattan minimum antara perkataan input 16-bit dan perkataan rujukan yang disimpan 16-bit. Kawasan cip berkesan, kelewatan pensuisan dan pelesapan kuasa penambah penuh empat nilai baharu, yang merupakan komponen utama VLSI logik dalam memori yang dicadangkan, masing-masing dikurangkan kepada kira-kira 33 peratus, 67 peratus dan 24 peratus. , berbanding dengan pelaksanaan CMOS binari yang sepadan di bawah teknologi EEPROM kilat 0.5-µm.
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Salinan
Takahiro HANYU, Michitaka KAMEYAMA, "Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1662-1668, September 1999, doi: .
Abstract: A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1662/_p
Salinan
@ARTICLE{e82-c_9_1662,
author={Takahiro HANYU, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic},
year={1999},
volume={E82-C},
number={9},
pages={1662-1668},
abstract={A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.},
keywords={},
doi={},
ISSN={},
month={September},}
Salinan
TY - JOUR
TI - Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 1662
EP - 1668
AU - Takahiro HANYU
AU - Michitaka KAMEYAMA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.
ER -