The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pemproses pengkuantitian vektor analog telah direka bentuk berdasarkan teknologi neuron-MOS (νMOS). Untuk mencapai ketumpatan penyepaduan yang tinggi, maklumat templat digabungkan ke dalam sel padanan (litar nilai mutlak) menggunakan teknologi ROM νMOS. Litar pemenang-ambil-semua (WTA) seni bina baharu νMOS digunakan untuk carian selari sepenuhnya untuk vektor jarak minimum. WTA melakukan carian pemenang berbilang resolusi dengan kawalan perolehan maklum balas automatik. Cip ujian yang mempunyai 256 vektor templat tetap 16 elemen telah dibina dalam teknologi CMOS dwi-polisilikon 1.5-µm dengan saiz cip 7.2 mm
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Salinan
Akira NAKADA, Masahiro KONDA, Tatsuo MORIMOTO, Takemi YONEZAWA, Tadashi SHIBATA, Tadahiro OHMI, "Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1730-1738, September 1999, doi: .
Abstract: An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1730/_p
Salinan
@ARTICLE{e82-c_9_1730,
author={Akira NAKADA, Masahiro KONDA, Tatsuo MORIMOTO, Takemi YONEZAWA, Tadashi SHIBATA, Tadahiro OHMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology},
year={1999},
volume={E82-C},
number={9},
pages={1730-1738},
abstract={An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm
keywords={},
doi={},
ISSN={},
month={September},}
Salinan
TY - JOUR
TI - Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1730
EP - 1738
AU - Akira NAKADA
AU - Masahiro KONDA
AU - Tatsuo MORIMOTO
AU - Takemi YONEZAWA
AU - Tadashi SHIBATA
AU - Tadahiro OHMI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm
ER -