The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini memperkatakan skim jam kuasa rendah baharu untuk litar logik dinamik untuk mengurangkan pelesapan kuasa. Walaupun skema jam konvensional untuk litar logik dinamik digunakan terutamanya untuk aplikasi berkelajuan tinggi seperti litar domino, arus puncaknya adalah sangat besar disebabkan oleh kepekatan pracas dan nyahcas dalam tempoh yang singkat. Adalah sukar bagi skim ini untuk mencapai kedua-dua pengurangan pelesapan kuasa dan prestasi tinggi pada masa yang sama. Dalam bidang kejuruteraan kuasa, kuasa meratakan bermaksud mengurangkan kuasa puncak ke puncak dengan mengekalkan jumlahnya. Oleh itu, kami mencadangkan skim jam yang canggih meratakan pelesapan kuasa elemen pemprosesan yang terutamanya mengurangkan pelesapan kuasa pemacu jam. Skim jam yang dicadangkan kami menggunakan jam yang tertindih dengan kawalan kuasa butiran halus, dan arus puncak menjadi lebih rendah dan pelesapan kuasa dalam tempoh singkat disamakan tanpa penalti prestasi kelajuan. Skim cadangan kami digunakan pada pengganda tatasusunan 4-bit, dan pengurangan pelesapan kuasa kedua-dua pengganda dan pemacu jam diukur oleh simulator HSPICE berdasarkan teknologi CMOS 0.5 µm. Ia ditunjukkan bahawa pelesapan kuasa pemacu jam, pengganda tatasusunan 4-bit, dan jumlahnya masing-masing berkurangan kira-kira 13.2 peratus, 2.6 peratus dan 7.0 peratus. Akibatnya, skim jam kami berkesan dalam mengurangkan pelesapan kuasa pemacu jam.
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Salinan
Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, "A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1733-1738, November 2000, doi: .
Abstract: This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1733/_p
Salinan
@ARTICLE{e83-c_11_1733,
author={Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits},
year={2000},
volume={E83-C},
number={11},
pages={1733-1738},
abstract={This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1733
EP - 1738
AU - Hiroyuki MATSUBARA
AU - Takahiro WATANABE
AU - Tadao NAKAMURA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.
ER -