The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kami mencadangkan get logik NAND universal berdasarkan logik kuantum fluks tunggal (SFQ). Gerbang NAND membolehkan pembinaan mana-mana litar logik. Dalam gerbang yang dicadangkan, tiga gelung superkonduktor berkongsi dua simpang Josephson (JJ). Arus kritikal JJ telah direka untuk membolehkan setiap dua gelung memerangkap SFQ pada masa yang sama. Kami mensimulasikan operasi dinamik get NAND ini. Keputusan menunjukkan bahawa get NAND boleh beroperasi dengan masa tunda 45 ps, dan penggunaan kuasa litar ini hampir kepada 0.06 µW/gate.
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Salinan
Hiroaki MYOREN, Seiichiro ONO, Susumu TAKADA, "NAND Gate for SFQ Logic Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 1, pp. 81-84, January 2000, doi: .
Abstract: We propose a universal NAND logic gate based on single flux quantum (SFQ) logic. The NAND gate enables the construction of any logic circuits. In the proposed gate, three superconducting loops share two Josephson junctions (JJs). The critical currents of the JJs were designed to allow each of any two loops to trap an SFQ at the same time. We simulated dynamic operation of this NAND gate. The results show that the NAND gate can operate with a delay time of 45 ps, and the power consumption of this circuit is close to 0.06 µW/gate.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_1_81/_p
Salinan
@ARTICLE{e83-c_1_81,
author={Hiroaki MYOREN, Seiichiro ONO, Susumu TAKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={NAND Gate for SFQ Logic Circuits},
year={2000},
volume={E83-C},
number={1},
pages={81-84},
abstract={We propose a universal NAND logic gate based on single flux quantum (SFQ) logic. The NAND gate enables the construction of any logic circuits. In the proposed gate, three superconducting loops share two Josephson junctions (JJs). The critical currents of the JJs were designed to allow each of any two loops to trap an SFQ at the same time. We simulated dynamic operation of this NAND gate. The results show that the NAND gate can operate with a delay time of 45 ps, and the power consumption of this circuit is close to 0.06 µW/gate.},
keywords={},
doi={},
ISSN={},
month={January},}
Salinan
TY - JOUR
TI - NAND Gate for SFQ Logic Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 81
EP - 84
AU - Hiroaki MYOREN
AU - Seiichiro ONO
AU - Susumu TAKADA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2000
AB - We propose a universal NAND logic gate based on single flux quantum (SFQ) logic. The NAND gate enables the construction of any logic circuits. In the proposed gate, three superconducting loops share two Josephson junctions (JJs). The critical currents of the JJs were designed to allow each of any two loops to trap an SFQ at the same time. We simulated dynamic operation of this NAND gate. The results show that the NAND gate can operate with a delay time of 45 ps, and the power consumption of this circuit is close to 0.06 µW/gate.
ER -