The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Makalah ini menerangkan tatasusunan get SOI-CMOS 0.35µm menggunakan transistor separa habis. Tatasusunan gerbang menggunakan teknik pengasingan medan-perisai dengan struktur terikat badan untuk menyekat masalah badan terapung seperti: (1) ciri-ciri kekusutan dalam arus longkang, (2) voltan pecah rendah, dan (3) kelewatan bergantung kepada frekuensi masa. Dengan mengoptimumkan susun atur sel asas dan pendawaian talian kuasa, tatasusunan get SOI-CMOS juga membenarkan penggunaan perpustakaan sel dan metodologi reka bentuk yang serasi dengan tatasusunan get CMOS pukal. LSI pemprosesan lapisan fizikal ATM (Mod Pemindahan Asynchronous) telah direka menggunakan tatasusunan get SOI-CMOS 0.35µm dengan 560k get mentah. LSI beroperasi pada 156 Mbps pada 2.0 V, sambil menggunakan kuasa 71% kurang daripada menggunakan tatasusunan get pukal-CMOS 0.35µm 3.3 V biasa.
Kimio UEDA
Koji NII
Yoshiki WADA
Shigenobu MAEDA
Toshiaki IWAMATSU
Yasuo YAMAGUCHI
Takashi IPPOSHI
Shigeto MAEGAWA
Koichiro MASHIKO
Yasutaka HORIBA
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Kimio UEDA, Koji NII, Yoshiki WADA, Shigenobu MAEDA, Toshiaki IWAMATSU, Yasuo YAMAGUCHI, Takashi IPPOSHI, Shigeto MAEGAWA, Koichiro MASHIKO, Yasutaka HORIBA, "A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 205-211, February 2000, doi: .
Abstract: This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_205/_p
Salinan
@ARTICLE{e83-c_2_205,
author={Kimio UEDA, Koji NII, Yoshiki WADA, Shigenobu MAEDA, Toshiaki IWAMATSU, Yasuo YAMAGUCHI, Takashi IPPOSHI, Shigeto MAEGAWA, Koichiro MASHIKO, Yasutaka HORIBA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors},
year={2000},
volume={E83-C},
number={2},
pages={205-211},
abstract={This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 205
EP - 211
AU - Kimio UEDA
AU - Koji NII
AU - Yoshiki WADA
AU - Shigenobu MAEDA
AU - Toshiaki IWAMATSU
AU - Yasuo YAMAGUCHI
AU - Takashi IPPOSHI
AU - Shigeto MAEGAWA
AU - Koichiro MASHIKO
AU - Yasutaka HORIBA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.
ER -