The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini melaporkan hasil aplikasi pemodelan proses/peranti termaju terkini kepada penyelesaian reka bentuk CMOS 0.13 [µm]. Telah ditunjukkan bahawa kedalaman simpang sambungan S/D, profil telaga, profil saluran dan arus pemacu CMOS 0.13 [µm] boleh diramalkan dengan ketepatan yang munasabah. Penambahbaikan model selanjutnya diperlukan untuk meramalkan ciri ΔL dan Vt-Lg bagi peranti dengan poket I/I senget dengan lebih tepat. Ia agak berfaedah untuk membina beberapa peta reka bentuk dengan menggunakan TCAD termaju yang canggih dengan cara 'pengeboman permaidani' pada peringkat awal pembangunan CMOS generasi baharu.
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Salinan
Shigetaka KUMASHIRO, "Advanced Process/Device Modeling and Its Impact on the CMOS Design Solution" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 8, pp. 1281-1287, August 2000, doi: .
Abstract: This paper reports the application results of the state-of-the-art advanced process/device modeling to the 0.13 [µm] CMOS design solution. It has been demonstrated that the S/D-extension junction depth, the well profile, the channel profile and the drive current of the 0.13 [µm] CMOS can be predicted with reasonable accuracy. Further model improvement is required to predict the ΔL and the Vt-Lg characteristics of the devices with the tilted pocket I/I more accurately. It is quite beneficial to construct several design maps by using the state-of-the-art advanced TCAD in a 'carpet bombing' way in the early stage of the development of new generation CMOS.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_8_1281/_p
Salinan
@ARTICLE{e83-c_8_1281,
author={Shigetaka KUMASHIRO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Advanced Process/Device Modeling and Its Impact on the CMOS Design Solution},
year={2000},
volume={E83-C},
number={8},
pages={1281-1287},
abstract={This paper reports the application results of the state-of-the-art advanced process/device modeling to the 0.13 [µm] CMOS design solution. It has been demonstrated that the S/D-extension junction depth, the well profile, the channel profile and the drive current of the 0.13 [µm] CMOS can be predicted with reasonable accuracy. Further model improvement is required to predict the ΔL and the Vt-Lg characteristics of the devices with the tilted pocket I/I more accurately. It is quite beneficial to construct several design maps by using the state-of-the-art advanced TCAD in a 'carpet bombing' way in the early stage of the development of new generation CMOS.},
keywords={},
doi={},
ISSN={},
month={August},}
Salinan
TY - JOUR
TI - Advanced Process/Device Modeling and Its Impact on the CMOS Design Solution
T2 - IEICE TRANSACTIONS on Electronics
SP - 1281
EP - 1287
AU - Shigetaka KUMASHIRO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2000
AB - This paper reports the application results of the state-of-the-art advanced process/device modeling to the 0.13 [µm] CMOS design solution. It has been demonstrated that the S/D-extension junction depth, the well profile, the channel profile and the drive current of the 0.13 [µm] CMOS can be predicted with reasonable accuracy. Further model improvement is required to predict the ΔL and the Vt-Lg characteristics of the devices with the tilted pocket I/I more accurately. It is quite beneficial to construct several design maps by using the state-of-the-art advanced TCAD in a 'carpet bombing' way in the early stage of the development of new generation CMOS.
ER -