The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kami telah menyiasat secara kuantitatif dan sistematik kesan induktansi parasit pada litar kuantum fluks tunggal cepat (RSFQ) melalui simulasi berangka. Walaupun kearuhan parasit selari dengan persimpangan hampir tidak mempunyai kesan ke atas prestasi litar, kearuhan parasit dalam siri dengan persimpangan dengan ketara mengurangkan margin operasi dan kelajuan litar yang telah dioptimumkan dengan andaian bahawa tiada kearuhan parasit wujud. Untuk meningkatkan margin dan kelajuan yang dikurangkan, kami telah mengoptimumkan semula litar untuk operasi dengan kearuhan parasit. Walaupun kelajuan dipertingkatkan secukupnya dengan prosedur pengoptimuman semula, margin tidak mencapai mereka yang tidak mempunyai parasit. Ini menunjukkan bahawa induktansi parasit mengecilkan kawasan operasi litar dan penambahbaikan margin dengan menukar hanya nilai parameter adalah terhad. Untuk penambahbaikan margin selanjutnya adalah penting untuk menggunakan proses dan susun atur yang meminimumkan kearuhan parasit siri.
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Salinan
Masaaki MAEZAWA, "Numerical Study of the Effect of Parasitic Inductance on RSFQ Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 1, pp. 20-28, January 2001, doi: .
Abstract: We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_1_20/_p
Salinan
@ARTICLE{e84-c_1_20,
author={Masaaki MAEZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Numerical Study of the Effect of Parasitic Inductance on RSFQ Circuits},
year={2001},
volume={E84-C},
number={1},
pages={20-28},
abstract={We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.},
keywords={},
doi={},
ISSN={},
month={January},}
Salinan
TY - JOUR
TI - Numerical Study of the Effect of Parasitic Inductance on RSFQ Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 20
EP - 28
AU - Masaaki MAEZAWA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2001
AB - We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.
ER -