The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Seni bina 64-bit untuk pemproses terbenam yang disasarkan untuk produk pengguna digital generasi akan datang telah dibangunkan. Ia mempunyai set arahan dwi-mod dan dioptimumkan untuk prestasi multimedia yang tinggi, yang disediakan oleh SIMD/arahan vektor titik terapung dalam ISA panjang 32-bit, dan saiz kod kecil, yang disediakan oleh ISA panjang 16-bit konvensional. Fail daftar besar, (64
Kunio UCHIYAMA
Fumio ARAKAWA
Yasuhiko SAITO
Koki NOGUCHI
Atsushi HASEGAWA
Shinichi YOSHIOKA
Naohiko IRIE
Takeshi KITAHARA
Mark DEBBAGE
Andy STURGES
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Kunio UCHIYAMA, Fumio ARAKAWA, Yasuhiko SAITO, Koki NOGUCHI, Atsushi HASEGAWA, Shinichi YOSHIOKA, Naohiko IRIE, Takeshi KITAHARA, Mark DEBBAGE, Andy STURGES, "Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 139-149, February 2001, doi: .
Abstract: A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (64
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_139/_p
Salinan
@ARTICLE{e84-c_2_139,
author={Kunio UCHIYAMA, Fumio ARAKAWA, Yasuhiko SAITO, Koki NOGUCHI, Atsushi HASEGAWA, Shinichi YOSHIOKA, Naohiko IRIE, Takeshi KITAHARA, Mark DEBBAGE, Andy STURGES, },
journal={IEICE TRANSACTIONS on Electronics},
title={Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products},
year={2001},
volume={E84-C},
number={2},
pages={139-149},
abstract={A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (64
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products
T2 - IEICE TRANSACTIONS on Electronics
SP - 139
EP - 149
AU - Kunio UCHIYAMA
AU - Fumio ARAKAWA
AU - Yasuhiko SAITO
AU - Koki NOGUCHI
AU - Atsushi HASEGAWA
AU - Shinichi YOSHIOKA
AU - Naohiko IRIE
AU - Takeshi KITAHARA
AU - Mark DEBBAGE
AU - Andy STURGES
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (64
ER -