The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini menerangkan skema perisian terbenam untuk pengekod MPEG-2 cip tunggal yang melaksanakan pengekodan video, audio dan sistem serentak dalam masa nyata. Perisian ini mempunyai struktur modul berskala, yang disusun secara hierarki dan mempunyai modul pemalam yang boleh dikembangkan. Untuk meningkatkan kebolehgunaan, beberapa modul tugasan disediakan untuk pemprosesan video, audio dan sistem masing-masing. Di samping itu, skim pengurusan tugas yang berkesan yang menampilkan pengundian dan penukaran tugas berasaskan gangguan telah dicadangkan untuk mencapai operasi masa nyata. Perisian yang mempunyai ciri ini dan termasuk semua modul tugas dilaksanakan pada pemproses media tunggal D30V pada satu cip MPEG-2 video, audio dan pengekod sistem. Pengekod ini merealisasikan pengekodan video MPEG-2 masa nyata, pengekodan audio Dolby Digital atau MPEG-1 dan pengekodan sistem yang menjana TS atau PS melebihi 50 Mbps untuk pelbagai aplikasi. Dengan mengandaikan sistem pengekod DVD atau DTV, perisian ini dibina semula dengan kurang daripada 56.6-kbait arahan dan prestasi 145.6 MIPS. Pemproses media tunggal dengan 64-kbait RAM arahan dan prestasi 162 MIPS, berjalan pada kadar jam 162 MHz, boleh berjaya mencapai operasi masa nyata dengan perisian terbenam yang dicadangkan.
Hiroshi SEGAWA
Yoshinori MATSUURA
Satoshi KUMAKI
Tetsuya MATSUMURA
Stefan SCOTZNIOVSKY
Shu MURAYAMA
Tetsuro WADA
Ayako HARADA
Eiji OHARA
Ken-ichi ASANO
Toyohiko YOSHIDA
Yasutaka HORIBA
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Salinan
Hiroshi SEGAWA, Yoshinori MATSUURA, Satoshi KUMAKI, Tetsuya MATSUMURA, Stefan SCOTZNIOVSKY, Shu MURAYAMA, Tetsuro WADA, Ayako HARADA, Eiji OHARA, Ken-ichi ASANO, Toyohiko YOSHIDA, Yasutaka HORIBA, "An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 202-211, February 2001, doi: .
Abstract: This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_202/_p
Salinan
@ARTICLE{e84-c_2_202,
author={Hiroshi SEGAWA, Yoshinori MATSUURA, Satoshi KUMAKI, Tetsuya MATSUMURA, Stefan SCOTZNIOVSKY, Shu MURAYAMA, Tetsuro WADA, Ayako HARADA, Eiji OHARA, Ken-ichi ASANO, Toyohiko YOSHIDA, Yasutaka HORIBA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core},
year={2001},
volume={E84-C},
number={2},
pages={202-211},
abstract={This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core
T2 - IEICE TRANSACTIONS on Electronics
SP - 202
EP - 211
AU - Hiroshi SEGAWA
AU - Yoshinori MATSUURA
AU - Satoshi KUMAKI
AU - Tetsuya MATSUMURA
AU - Stefan SCOTZNIOVSKY
AU - Shu MURAYAMA
AU - Tetsuro WADA
AU - Ayako HARADA
AU - Eiji OHARA
AU - Ken-ichi ASANO
AU - Toyohiko YOSHIDA
AU - Yasutaka HORIBA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.
ER -