The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Teknologi denyar poli tunggal yang sangat dipercayai bernama ie-Flash (Denyar elektrod get songsang), yang boleh dibenamkan dalam proses CMOS standard tanpa sebarang pengubahsuaian proses, telah dibangunkan. Sel kilat ie terdiri daripada dua sel asas untuk bacaan OR-logik, menghasilkan peningkatan kebolehpercayaan yang ketara. 5 Pengaturcaraan V dengan tempoh 1 ms dan operasi 1.2 V-baca modul memori 35 bit yang direka oleh proses CMOS 0.14 µm ditunjukkan. Teknologi denyar ini bukan sahaja akan memanjangkan pengurangan kos ujian sistem pada cip dengan menggantikan pautan laser tetapi juga menyediakan fleksibiliti aplikasi logik boleh atur cara.
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Salinan
Shoji SHUKURI, Kazumasa YANAGISAWA, Koichiro ISHIBASHI, "CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 6, pp. 734-739, June 2001, doi: .
Abstract: A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_6_734/_p
Salinan
@ARTICLE{e84-c_6_734,
author={Shoji SHUKURI, Kazumasa YANAGISAWA, Koichiro ISHIBASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip},
year={2001},
volume={E84-C},
number={6},
pages={734-739},
abstract={A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip
T2 - IEICE TRANSACTIONS on Electronics
SP - 734
EP - 739
AU - Shoji SHUKURI
AU - Kazumasa YANAGISAWA
AU - Koichiro ISHIBASHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2001
AB - A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.
ER -