The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Memori akses rawak ferroelektrik rantai (FeRAM rantai) ialah penyelesaian untuk memori tak meruap berketumpatan tinggi dan berkelajuan tinggi pada masa hadapan. Satu sel memori terdiri daripada satu transistor dan satu kapasitor ferroelektrik yang disambung secara selari, dan satu blok sel memori terdiri daripada sel majmuk dan satu blok memilih transistor secara bersiri. Konfigurasi ini merealisasikan sel memori kecil sebanyak 4F2 saiz dan masa capaian rawak yang cepat. Makalah ini menunjukkan gambaran keseluruhan dan trend seni bina FeRAM rantai. Pertama, konsep rantai FeRAM dibentangkan, dan operasi asas termasuk dua skim pemanduan plat sel dibincangkan. Kedua, dengan mengandaikan penjanaan berbilang megabit, ciri dan prestasi ideal dibincangkan dari segi saiz cetakan, kelajuan dan aspek lain. Ketiga, prototaip rantai FeRAM dan struktur sel praktikal untuk memori berskala megabit menggunakan proses CMOS 0.5-logam 2 µm ditunjukkan. Dengan memperkenalkan teknik pemacu plat sel yang pantas dan padat, prototaip ini mencapai masa capaian rawak 37-ns dan masa kitaran baca/tulis 80-ns, yang merupakan kelajuan terpantas yang dilaporkan untuk FeRAM. Keempat, selepas membincangkan trend sel memori masa hadapan dan masalah berkenaan dengan FeRAM berskala, pendekatan blok sel keuntungan untuk FeRAM rantaian skala gigabit masa hadapan diperkenalkan. Ini menyedari kedua-dua saiz sel purata yang kecil dan isyarat sel yang besar walaupun pada polarisasi sel kecil.
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Salinan
Daisaburo TAKASHIMA, "Overview and Trend of Chain FeRAM Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 6, pp. 747-756, June 2001, doi: .
Abstract: A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of plural cells and a block selecting transistor in series. This configuration realizes small memory cell of 4F2 size and fast random access time. This paper shows an overview and trend of chain FeRAM architecture. First, the concept of chain FeRAM is presented, and basic operations including two cell-plate driving schemes are discussed. Second, assuming multi-megabit generation, ideal features and performances are discussed in terms of die size, speed and other aspects. Third, the prototype of chain FeRAM and the practical cell structure for megabit-scale memories using 0.5 µ m 2-metal CMOS process are demonstrated. By introducing fast and compact cell-plate drive technique, this prototype achieves random access time of 37-ns and read/write cycle time of 80-ns, which are the fastest speeds reported for FeRAMs. Fourth, after discussing future memory cell trend and problems respecting scaled FeRAMs, a gain cell block approach for future gigabit-scale chain FeRAMs is introduced. This realizes both a small average cell size and a large cell signal even at small cell polarization.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_6_747/_p
Salinan
@ARTICLE{e84-c_6_747,
author={Daisaburo TAKASHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Overview and Trend of Chain FeRAM Architecture},
year={2001},
volume={E84-C},
number={6},
pages={747-756},
abstract={A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of plural cells and a block selecting transistor in series. This configuration realizes small memory cell of 4F2 size and fast random access time. This paper shows an overview and trend of chain FeRAM architecture. First, the concept of chain FeRAM is presented, and basic operations including two cell-plate driving schemes are discussed. Second, assuming multi-megabit generation, ideal features and performances are discussed in terms of die size, speed and other aspects. Third, the prototype of chain FeRAM and the practical cell structure for megabit-scale memories using 0.5 µ m 2-metal CMOS process are demonstrated. By introducing fast and compact cell-plate drive technique, this prototype achieves random access time of 37-ns and read/write cycle time of 80-ns, which are the fastest speeds reported for FeRAMs. Fourth, after discussing future memory cell trend and problems respecting scaled FeRAMs, a gain cell block approach for future gigabit-scale chain FeRAMs is introduced. This realizes both a small average cell size and a large cell signal even at small cell polarization.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - Overview and Trend of Chain FeRAM Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 747
EP - 756
AU - Daisaburo TAKASHIMA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2001
AB - A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of plural cells and a block selecting transistor in series. This configuration realizes small memory cell of 4F2 size and fast random access time. This paper shows an overview and trend of chain FeRAM architecture. First, the concept of chain FeRAM is presented, and basic operations including two cell-plate driving schemes are discussed. Second, assuming multi-megabit generation, ideal features and performances are discussed in terms of die size, speed and other aspects. Third, the prototype of chain FeRAM and the practical cell structure for megabit-scale memories using 0.5 µ m 2-metal CMOS process are demonstrated. By introducing fast and compact cell-plate drive technique, this prototype achieves random access time of 37-ns and read/write cycle time of 80-ns, which are the fastest speeds reported for FeRAMs. Fourth, after discussing future memory cell trend and problems respecting scaled FeRAMs, a gain cell block approach for future gigabit-scale chain FeRAMs is introduced. This realizes both a small average cell size and a large cell signal even at small cell polarization.
ER -