The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Skim baca/tulis ayunan talian data kecil diterangkan untuk separuh-Vcc DRAM tak meruap plat dengan kapasitor ferroelektrik direka untuk mencapai kebolehpercayaan yang tinggi untuk operasi baca/tulis. Dalam skema ini, operasi baca/tulis biasa memegang data sebagai caj dengan ayunan talian-data yang kecil, dan operasi stor menyediakan polarisasi yang mencukupi dengan ayunan talian-data penuh. Skim ini membolehkan daya tahan baca/tulis yang tinggi, kerana ayunan talian data yang kecil mengurangkan keletihan kapasitor ferroelektrik. Dua teknologi litar digunakan dalam skim ini untuk meningkatkan margin operasi. Yang pertama ialah teknik kawalan voltan plat yang menyelesaikan masalah pengekalan polarisasi separuh-Vcc teknologi DRAM tidak meruap plat. Yang kedua ialah teknik penarikan semula kapasitans talian data berganda yang menghubungkan dua talian data ke sel dan membesarkan isyarat bacaan berbanding operasi biasa, apabila hanya satu talian data disambungkan ke sel. Teknik dan litar ini meningkatkan daya tahan kitaran tulis sebanyak hampir tiga urutan magnitud, sambil mengurangkan penggunaan kuasa tatasusunan semasa operasi baca/tulis kepada satu pertiga daripada DRAM tidak meruap konvensional.
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Salinan
Hiroki FUJISAWA, Takeshi SAKATA, Tomonori SEKIGUCHI, Kazuyoshi TORII, Katsutaka KIMURA, Kazuhiko KAJIGAYA, "A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 6, pp. 763-770, June 2001, doi: .
Abstract: A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_6_763/_p
Salinan
@ARTICLE{e84-c_6_763,
author={Hiroki FUJISAWA, Takeshi SAKATA, Tomonori SEKIGUCHI, Kazuyoshi TORII, Katsutaka KIMURA, Kazuhiko KAJIGAYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors},
year={2001},
volume={E84-C},
number={6},
pages={763-770},
abstract={A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
T2 - IEICE TRANSACTIONS on Electronics
SP - 763
EP - 770
AU - Hiroki FUJISAWA
AU - Takeshi SAKATA
AU - Tomonori SEKIGUCHI
AU - Kazuyoshi TORII
AU - Katsutaka KIMURA
AU - Kazuhiko KAJIGAYA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2001
AB - A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.
ER -