The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Sel memori ferroelektrik jenis 1T2C, di mana dua kapasitor ferroelektrik dengan luas yang sama disambungkan ke pintu MOSFET biasa dengan SiO2Antara muka /Si, telah direka dan dicirikan. Hubungan antara pelbagai parameter peranti dan ciri-ciri sel memori telah disiasat dengan menggunakan simulasi SPICE. Daripada hasil simulasi didapati bahawa tetingkap memori berubah dengan ketara oleh parameter peranti, yang bermaksud bahawa voltan operasi sel memori boleh dikawal dengan baik oleh parameter ini. Sel fabrikasi terdiri daripada struktur get bertindan Pt/SBT/Pt/Ti/SiO2/Si dengan nisbah luas kapasitor MOS (SO) kepada kapasitor ferroelektrik (SF) daripada 6 atau 10. Operasi memori tidak meruap telah disahkan, dan tetingkap memori yang diperolehi bertepatan dengan keputusan simulasi secara kualitatif. Tambahan pula, nisbah hidup/mati semasa dalam operasi baca keluar adalah lebih besar daripada 3-tertib-magnitud dan masa pengekalan data lebih lama daripada 6
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Salinan
Satoru OGASAWARA, Sung-Min YOON, Hiroshi ISHIWARA, "Fabrication and Characterization of 1T2C-Type Ferroelectric Memory Cell" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 6, pp. 771-776, June 2001, doi: .
Abstract: A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_6_771/_p
Salinan
@ARTICLE{e84-c_6_771,
author={Satoru OGASAWARA, Sung-Min YOON, Hiroshi ISHIWARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fabrication and Characterization of 1T2C-Type Ferroelectric Memory Cell},
year={2001},
volume={E84-C},
number={6},
pages={771-776},
abstract={A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - Fabrication and Characterization of 1T2C-Type Ferroelectric Memory Cell
T2 - IEICE TRANSACTIONS on Electronics
SP - 771
EP - 776
AU - Satoru OGASAWARA
AU - Sung-Min YOON
AU - Hiroshi ISHIWARA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2001
AB - A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6
ER -