The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Makalah ini mengkaji keputusan percubaan kami untuk sifat pengangkutan elektrik bagi transistor kesan medan-oksida-separa konduktor silikon skala nano (MOSFET). Kami menggunakan peranti yang sangat kecil yang dihasilkan menggunakan teknik litografi berskala 10-nm: MOSFET simpang cetek elektrik (EJ-MOSFET) dan transistor elektron panas sisi (LHET). Dengan LHET kami berjaya mengesan secara langsung arus elektron panas dan menganggarkan panjang ciri sekitar 25 nm. Kami juga menyiasat mekanisme kelonggaran tenaga dengan melakukan pengukuran pada pelbagai voltan dan suhu yang digunakan. Tambahan pula, kami dengan jelas memerhatikan arus terowong antara sumber dan longkang (terowong longkang sumber) dalam EJ-MOSFET 8-nm-gate-panjang. Berdasarkan keputusan eksperimen ini, kami meramalkan had pengecilan MOSFET adalah sekitar 5 nm dalam skema terowong longkang sumber.
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Salinan
Hisao KAWAURA, Toshitsugu SAKAMOTO, "Electrical Transport in Nano-Scale Silicon Devices" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1037-1042, August 2001, doi: .
Abstract: This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1037/_p
Salinan
@ARTICLE{e84-c_8_1037,
author={Hisao KAWAURA, Toshitsugu SAKAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Electrical Transport in Nano-Scale Silicon Devices},
year={2001},
volume={E84-C},
number={8},
pages={1037-1042},
abstract={This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.},
keywords={},
doi={},
ISSN={},
month={August},}
Salinan
TY - JOUR
TI - Electrical Transport in Nano-Scale Silicon Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 1037
EP - 1042
AU - Hisao KAWAURA
AU - Toshitsugu SAKAMOTO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.
ER -