The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kami mencadangkan teknik linearisasi untuk penguat MMIC. Perkara utama teknik ini ialah peningkatan lineariti MESFET rendah herotan rendah (LD-FET) yang baru dibangunkan dan dimaksimumkan IP3 dengan menggabungkan LD-FET dengan MESFET (D-FET) mod pengurangan keuntungan tinggi tanpa peningkatan penggunaan kuasa. LD-FET dicirikan oleh profil dopan saluran uniknya yang disediakan oleh yang dikebumikan p-jenis ion-implantasi dan berganda n-implantasi ion jenis dengan tenaga pecutan tinggi dan rendah. FET ini mencapai tingkah laku yang lebih rata dari segi kekonduksian bersama (gm) berbanding dengan MESFET konvensional tanpa mengira perubahan dalam voltan pincang pintu (Vgs). Proses penjajaran diri/implantasi ion terpilih membolehkan LD-FET dan D-FET dibuat secara serentak. Proses ini menggalakkan IP3 memaksimumkan penguat berbilang peringkat dengan menggabungkan kelebihan kedua-dua MESFET berciri berbeza dengan sewajarnya. Kami membuat dan menguji penguat MMIC dua peringkat yang sangat linear menggunakan teknik yang dicadangkan, dan mendapati bahawa nisbah intermodulasi tertib ketiganya (IMR) prestasi adalah 8.7 dB lebih baik daripada penguat MMIC konvensional pada tahap isyarat input -20 dBm tanpa peningkatan dalam pelesapan semasa. Konfigurasi yang dibina dengan menggunakan teknik yang dicadangkan sama-sama mengurangkan pelesapan semasa peringkat kedua kepada 1/2.72 kali ganda daripada konfigurasi konvensional, yang memerlukan D-FET 2.72 kali lebih besar pada peringkat kedua untuk mendapatkan 8.7-dB IMR penambahbaikan. Tambahan pula, kami dapat menambah baik IMR sebanyak 3.5 dB dengan mengoptimumkan keadaan pincang pintu untuk LD-FET. Keputusan ini mengesahkan kesahihan teknik yang dicadangkan.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Masashi NAKATSUGAWA, Masahiro MURAGUCHI, Yo YAMAGUCHI, "A Highly Linearized MMIC Amplifier Using a Combination of a Newly Developed LD-FET and D-FET Simultaneously Fabricated with a Self-Alignment/Selective Ion-Implantation Process" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 12, pp. 1981-1989, December 2002, doi: .
Abstract: We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_12_1981/_p
Salinan
@ARTICLE{e85-c_12_1981,
author={Masashi NAKATSUGAWA, Masahiro MURAGUCHI, Yo YAMAGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Highly Linearized MMIC Amplifier Using a Combination of a Newly Developed LD-FET and D-FET Simultaneously Fabricated with a Self-Alignment/Selective Ion-Implantation Process},
year={2002},
volume={E85-C},
number={12},
pages={1981-1989},
abstract={We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.},
keywords={},
doi={},
ISSN={},
month={December},}
Salinan
TY - JOUR
TI - A Highly Linearized MMIC Amplifier Using a Combination of a Newly Developed LD-FET and D-FET Simultaneously Fabricated with a Self-Alignment/Selective Ion-Implantation Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 1981
EP - 1989
AU - Masashi NAKATSUGAWA
AU - Masahiro MURAGUCHI
AU - Yo YAMAGUCHI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2002
AB - We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.
ER -