The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Teras pemproses terbenam menggunakan seni bina cawangan berpecah telah dibangunkan. Teras pemproses ini menyasarkan 400 MHz menggunakan teknologi 0.18 µm, dan frekuensi yang lebih tinggi memerlukan saluran paip yang lebih mendalam daripada pemproses konvensional. Untuk menyelesaikan masalah penalti cawangan yang semakin meningkat disebabkan oleh saluran paip yang lebih mendalam, pemproses ini menggunakan mekanisme pramuat aktif untuk pramuat arahan sasaran ke penimbal dalaman untuk menyembunyikan kependaman cache arahan. Pemproses juga menggunakan berbilang penimbal arahan untuk mengurangkan kitaran penalti cawangan bagi salah ramal cawangan. Keputusan anggaran prestasi menunjukkan bahawa kira-kira 70% daripada kitaran overhed cawangan boleh dikurangkan daripada pelaksanaan konvensional. Kawasan untuk mekanisme cawangan ini menggunakan hanya 1% daripada jumlah teras, yang lebih kecil daripada skim penampan sasaran cawangan (BTB) konvensional, dan membantu mencapai kuasa rendah dan kos rendah.
Naohiko IRIE
Fumio ARAKAWA
Kunio UCHIYAMA
Shinichi YOSHIOKA
Atsushi HASEGAWA
Kevin IADONATE
Mark DEBBAGE
David SHEPHERD
Margaret GEARTY
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Salinan
Naohiko IRIE, Fumio ARAKAWA, Kunio UCHIYAMA, Shinichi YOSHIOKA, Atsushi HASEGAWA, Kevin IADONATE, Mark DEBBAGE, David SHEPHERD, Margaret GEARTY, "Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 315-322, February 2002, doi: .
Abstract: An embedded processor core using split branch architecture has been developed. This processor core targets 400 MHz using 0.18 µm technology, and its higher frequency needs deeper pipeline than the conventional processor. To solve the increasing branch penalty problem caused by a deeper pipeline, this processor takes an active preload mechanism to preload the target instructions to internal buffers in order to hide the instruction cache latency. The processor also uses multiple instruction buffers to reduce branch penalty cycles of branch misprediction. The performance estimation result shows that about 70% of branch overhead cycles can be reduced from the conventional implementation. The area for this branch mechanism consumes only 1% of the total core, which is smaller than the conventional branch target buffer (BTB) scheme, and helps to achieve low power and low cost.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_315/_p
Salinan
@ARTICLE{e85-c_2_315,
author={Naohiko IRIE, Fumio ARAKAWA, Kunio UCHIYAMA, Shinichi YOSHIOKA, Atsushi HASEGAWA, Kevin IADONATE, Mark DEBBAGE, David SHEPHERD, Margaret GEARTY, },
journal={IEICE TRANSACTIONS on Electronics},
title={Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products},
year={2002},
volume={E85-C},
number={2},
pages={315-322},
abstract={An embedded processor core using split branch architecture has been developed. This processor core targets 400 MHz using 0.18 µm technology, and its higher frequency needs deeper pipeline than the conventional processor. To solve the increasing branch penalty problem caused by a deeper pipeline, this processor takes an active preload mechanism to preload the target instructions to internal buffers in order to hide the instruction cache latency. The processor also uses multiple instruction buffers to reduce branch penalty cycles of branch misprediction. The performance estimation result shows that about 70% of branch overhead cycles can be reduced from the conventional implementation. The area for this branch mechanism consumes only 1% of the total core, which is smaller than the conventional branch target buffer (BTB) scheme, and helps to achieve low power and low cost.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products
T2 - IEICE TRANSACTIONS on Electronics
SP - 315
EP - 322
AU - Naohiko IRIE
AU - Fumio ARAKAWA
AU - Kunio UCHIYAMA
AU - Shinichi YOSHIOKA
AU - Atsushi HASEGAWA
AU - Kevin IADONATE
AU - Mark DEBBAGE
AU - David SHEPHERD
AU - Margaret GEARTY
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - An embedded processor core using split branch architecture has been developed. This processor core targets 400 MHz using 0.18 µm technology, and its higher frequency needs deeper pipeline than the conventional processor. To solve the increasing branch penalty problem caused by a deeper pipeline, this processor takes an active preload mechanism to preload the target instructions to internal buffers in order to hide the instruction cache latency. The processor also uses multiple instruction buffers to reduce branch penalty cycles of branch misprediction. The performance estimation result shows that about 70% of branch overhead cycles can be reduced from the conventional implementation. The area for this branch mechanism consumes only 1% of the total core, which is smaller than the conventional branch target buffer (BTB) scheme, and helps to achieve low power and low cost.
ER -