The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan HiperSonic 1, pemproses isyarat berbilang standard, khusus aplikasi, yang direka untuk melaksanakan algoritma penukaran jalur asas dalam aplikasi LAN wayarles 802.11 GHz berasaskan IEEE2a dan HIPERLAN/5. Berbeza dengan pelaksanaan khusus yang sedia ada secara meluas, kebanyakan usaha pengiraan di sini dipetakan pada teras DSP yang boleh dikonfigurasikan, data dan selari arahan. Teras ditambah dengan isyarat campuran A/D, penukar D/A dan pemecut perkakasan. Seni bina memori dan daftar, set arahan dan antara muka persisian cip telah dioptimumkan dengan teliti untuk aplikasi yang disasarkan, yang membawa kepada gabungan bunyi fleksibiliti, kawasan mati dan penggunaan kuasa. Penyelesaian transistor 120 MHz, 7.6 juta telah dilaksanakan dalam CMOS 0.18 µm dan melaksanakan pemprosesan jalur asas yang mematuhi IEEE802.11a atau HiperLAN/2 pada kadar data sehingga 60 Mbit/s.
Johannes KNEIP
Matthias WEISS
Wolfram DRESCHER
Volker AUE
Jurgen STROBEL
Thomas OBERTHUR
Michael BOLLE
Gerhard FETTWEIS
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Salinan
Johannes KNEIP, Matthias WEISS, Wolfram DRESCHER, Volker AUE, Jurgen STROBEL, Thomas OBERTHUR, Michael BOLLE, Gerhard FETTWEIS, "Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 359-367, February 2002, doi: .
Abstract: This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_359/_p
Salinan
@ARTICLE{e85-c_2_359,
author={Johannes KNEIP, Matthias WEISS, Wolfram DRESCHER, Volker AUE, Jurgen STROBEL, Thomas OBERTHUR, Michael BOLLE, Gerhard FETTWEIS, },
journal={IEICE TRANSACTIONS on Electronics},
title={Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications},
year={2002},
volume={E85-C},
number={2},
pages={359-367},
abstract={This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 359
EP - 367
AU - Johannes KNEIP
AU - Matthias WEISS
AU - Wolfram DRESCHER
AU - Volker AUE
AU - Jurgen STROBEL
AU - Thomas OBERTHUR
AU - Michael BOLLE
AU - Gerhard FETTWEIS
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.
ER -