The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Peningkatan mobiliti lapisan penyongsangan dan kapasitans lapisan penyongsangan menjadi lebih penting dalam merealisasikan CMOS berskala, dari kedua-dua sudut pandangan prestasi yang lebih tinggi dan penggunaan kuasa yang lebih rendah. Kertas kerja ini membentangkan senario kejuruteraan struktur subband dalam lapisan penyongsangan untuk peningkatan mobiliti lapisan penyongsangan dan kapasiti dalam MOSFET. Faktor utama untuk peningkatan mobiliti elektron adalah untuk meningkatkan perbezaan tenaga dalam tenaga subband antara lembah dua lipatan dan empat lipatan dan penghunian elektron terhasil daripada lembah dua lipatan. Ciri-ciri elektrik dua struktur peranti berdasarkan kejuruteraan subband ini, MOSFET-Si tegang dan MOSFET SOI ultra-nipis, dikaji. Juga, ditunjukkan bahawa pengurangan dalam filem SOI kepada kurang daripada ketebalan lapisan penyongsangan MOSFET pukal adalah cara yang berkesan untuk meningkatkan kapasitans lapisan penyongsangan.
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Salinan
Shin-ichi TAKAGI, "Subband Structure Engineering for Realizing Scaled CMOS with High Performance and Low Power Consumption" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1064-1072, May 2002, doi: .
Abstract: Enhancement of inversion-layer mobility and inversion-layer capacitance becomes more important in realizing scaled CMOS, from both viewpoints of higher performance and lower power consumption. This paper presents an engineering scenario of the subband structure in inversion layer for the enhancement of inversion-layer mobility and capacitance in MOSFETs. A key factor for the electron mobility enhancement is to increase the energy difference in the subband energy between the two-fold and the four-fold valleys and the resultant electron occupancy of the two-fold valleys. The electrical characteristics of two device structures based on this subband engineering, strained-Si MOSFETs and ultra-thin SOI MOSFETs, are studied. Also, it is shown that the reduction in SOI films down to less than inversion-layer thickness of bulk MOSFETs is an effective way to increase inversion-layer capacitance.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1064/_p
Salinan
@ARTICLE{e85-c_5_1064,
author={Shin-ichi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Subband Structure Engineering for Realizing Scaled CMOS with High Performance and Low Power Consumption},
year={2002},
volume={E85-C},
number={5},
pages={1064-1072},
abstract={Enhancement of inversion-layer mobility and inversion-layer capacitance becomes more important in realizing scaled CMOS, from both viewpoints of higher performance and lower power consumption. This paper presents an engineering scenario of the subband structure in inversion layer for the enhancement of inversion-layer mobility and capacitance in MOSFETs. A key factor for the electron mobility enhancement is to increase the energy difference in the subband energy between the two-fold and the four-fold valleys and the resultant electron occupancy of the two-fold valleys. The electrical characteristics of two device structures based on this subband engineering, strained-Si MOSFETs and ultra-thin SOI MOSFETs, are studied. Also, it is shown that the reduction in SOI films down to less than inversion-layer thickness of bulk MOSFETs is an effective way to increase inversion-layer capacitance.},
keywords={},
doi={},
ISSN={},
month={May},}
Salinan
TY - JOUR
TI - Subband Structure Engineering for Realizing Scaled CMOS with High Performance and Low Power Consumption
T2 - IEICE TRANSACTIONS on Electronics
SP - 1064
EP - 1072
AU - Shin-ichi TAKAGI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - Enhancement of inversion-layer mobility and inversion-layer capacitance becomes more important in realizing scaled CMOS, from both viewpoints of higher performance and lower power consumption. This paper presents an engineering scenario of the subband structure in inversion layer for the enhancement of inversion-layer mobility and capacitance in MOSFETs. A key factor for the electron mobility enhancement is to increase the energy difference in the subband energy between the two-fold and the four-fold valleys and the resultant electron occupancy of the two-fold valleys. The electrical characteristics of two device structures based on this subband engineering, strained-Si MOSFETs and ultra-thin SOI MOSFETs, are studied. Also, it is shown that the reduction in SOI films down to less than inversion-layer thickness of bulk MOSFETs is an effective way to increase inversion-layer capacitance.
ER -