The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas ini, pam cas (CP) yang dipertingkatkan dan pengesan frekuensi fasa tak linear (PFD) diubah suai direka bentuk dan direka dalam proses CMOS 90-nm. CP dioptimumkan dengan gabungan teknik litar seperti skema pembatalan ralat alas untuk menghapuskan suntikan cas dan ciri-ciri lain yang tidak ideal. PFD tak linear adalah berdasarkan topologi litar yang diubah suai untuk meningkatkan keupayaan pemerolehan PLL. CP yang dioptimumkan dan PFD tak linear disepadukan ke dalam PLL Ka-band. Nisbah ketidakpadanan arus keluaran yang diukur bagi CP yang dipertingkatkan adalah kurang daripada 1% apabila voltan keluaran Vkeluar turun naik antara 0.2 hingga 1.1V daripada bekalan kuasa 1.2V. Julat pengesanan ralat fasa yang diukur bagi PFD tak linear yang diubah suai adalah antara -2π dan 2π. Disebabkan oleh CP dan PFD yang diubah suai, rangsangan rujukan terukur bagi pensintesis frekuensi PLL Ka-band yang mengandungi CP dan PFD yang dioptimumkan hanya -56.409dBc pada 30-GHz pada keadaan terkunci.
Lu TANG
Southeast University
Zhigong WANG
Southeast University
Tiantian FAN
Southeast University
Faen LIU
Southeast University
Changchun ZHANG
Nanjing University of Posts and Telecommunications
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Salinan
Lu TANG, Zhigong WANG, Tiantian FAN, Faen LIU, Changchun ZHANG, "Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 11, pp. 825-832, November 2019, doi: 10.1587/transele.2019ECP5007.
Abstract: In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECP5007/_p
Salinan
@ARTICLE{e102-c_11_825,
author={Lu TANG, Zhigong WANG, Tiantian FAN, Faen LIU, Changchun ZHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process},
year={2019},
volume={E102-C},
number={11},
pages={825-832},
abstract={In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.},
keywords={},
doi={10.1587/transele.2019ECP5007},
ISSN={1745-1353},
month={November},}
Salinan
TY - JOUR
TI - Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 825
EP - 832
AU - Lu TANG
AU - Zhigong WANG
AU - Tiantian FAN
AU - Faen LIU
AU - Changchun ZHANG
PY - 2019
DO - 10.1587/transele.2019ECP5007
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2019
AB - In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.
ER -