The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kemerosotan kecekapan litar penukar DC-AC berasaskan SiC-MOSFET disebabkan oleh penuaan peranti aktif elektrik disiasat. Model penuaan kompak yang baru dibangunkan HiSIM_HSiC untuk SiC-MOSFET voltan tinggi digunakan dalam penyiasatan. Model ini mempertimbangkan secara eksplisit peningkatan ketumpatan perangkap pembawa dalam penyelesaian persamaan Poisson. Ciri-ciri penukar yang diukur semasa kerosakan talian ke tanah (3LG) 3 fasa dihasilkan semula dengan betul oleh model. Ia disahkan bahawa MOSFET mengalami tekanan tambahan disebabkan oleh berat sebelah yang tinggi yang berlaku semasa kejadian kerosakan, yang diterjemahkan kepada penuaan MOSFET yang teruk. Keputusan simulasi meramalkan pengurangan kecekapan penukar sebanyak 0.5% disebabkan oleh 70ms-3LG tunggal, yang bersamaan dengan satu tahun operasi dalam keadaan biasa, di mana tiada tekanan tambahan dikenakan. Dengan model kompak yang dibangunkan, ramalan kemerosotan kecekapan litar penukar di bawah tegasan berpanjangan, yang mana pengukuran sukar diperoleh dan biasanya tidak tersedia, juga boleh dilaksanakan.
Kenshiro SATO
Hiroshima University
Dondee NAVARRO
Hiroshima University
Shinya SEKIZAKI
Hiroshima University
Yoshifumi ZOKA
Hiroshima University
Naoto YORINO
Hiroshima University
Hans Jürgen MATTAUSCH
Hiroshima University
Mitiko MIURA-MATTAUSCH
Hiroshima University
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Salinan
Kenshiro SATO, Dondee NAVARRO, Shinya SEKIZAKI, Yoshifumi ZOKA, Naoto YORINO, Hans Jürgen MATTAUSCH, Mitiko MIURA-MATTAUSCH, "Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 3, pp. 119-126, March 2020, doi: 10.1587/transele.2019ECP5010.
Abstract: The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECP5010/_p
Salinan
@ARTICLE{e103-c_3_119,
author={Kenshiro SATO, Dondee NAVARRO, Shinya SEKIZAKI, Yoshifumi ZOKA, Naoto YORINO, Hans Jürgen MATTAUSCH, Mitiko MIURA-MATTAUSCH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model},
year={2020},
volume={E103-C},
number={3},
pages={119-126},
abstract={The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.},
keywords={},
doi={10.1587/transele.2019ECP5010},
ISSN={1745-1353},
month={March},}
Salinan
TY - JOUR
TI - Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model
T2 - IEICE TRANSACTIONS on Electronics
SP - 119
EP - 126
AU - Kenshiro SATO
AU - Dondee NAVARRO
AU - Shinya SEKIZAKI
AU - Yoshifumi ZOKA
AU - Naoto YORINO
AU - Hans Jürgen MATTAUSCH
AU - Mitiko MIURA-MATTAUSCH
PY - 2020
DO - 10.1587/transele.2019ECP5010
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2020
AB - The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.
ER -