The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Prestasi penghala/suis rangkaian telah meningkat dengan ketara sejak beberapa dekad yang lalu dengan peningkatan trafik internet dan pusat data secara mendadak. Prestasi penghala sangat bergantung pada sistem ingatan, contohnya penampan paket berasaskan DRAM, yang selalunya mengehadkan kebolehskalaan penghala. Walau bagaimanapun, jurang yang semakin melebar antara bas I/O memori dan kelajuan tatasusunan sel memori dan lokaliti penimbal baris yang berkurangan daripada saluran dan bank yang semakin meningkat telah mengurangkan keuntungan prestasi daripada teknologi memori terkini seperti DDR4 atau HBM2 DRAM. Kerja-kerja sebelumnya meningkatkan lebar jalur memori dengan mengekalkan penimbal per baris gilir berasaskan SRAM atau penimbal input/output per bank dalam pengawal memori untuk menyokong penimbal paket berasaskan DRAM. Penampan menyimpan paket buat sementara waktu apabila konflik bank berlaku tetapi tidak dapat menghalang trafik yang mendorong gangguan daripada membelasah penampan baris DRAM. Dalam kajian ini, kami secara langsung mengintegrasikan SRAM ke dalam penimbal paket berasaskan DRAM dan memetakan paket tersebut yang merendahkan lokaliti penampan baris DRAM ke dalam SRAM. Ini memaksimumkan lokaliti dan keselarian akses DRAM. Skim yang dicadangkan boleh memanfaatkan mana-mana skim sedia ada. Keputusan eksperimen menunjukkan 22.41% peningkatan berbanding skim sedia ada terbaik untuk satu saluran dari segi penggunaan lebar jalur memori di bawah senario sesak yang teruk.
Yongwoon SONG
Sogang University
Dongkeon CHOI
Sogang University
Hyukjun LEE
Sogang University
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Salinan
Yongwoon SONG, Dongkeon CHOI, Hyukjun LEE, "Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 12, pp. 849-852, December 2019, doi: 10.1587/transele.2019ECS6003.
Abstract: The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECS6003/_p
Salinan
@ARTICLE{e102-c_12_849,
author={Yongwoon SONG, Dongkeon CHOI, Hyukjun LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers},
year={2019},
volume={E102-C},
number={12},
pages={849-852},
abstract={The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.},
keywords={},
doi={10.1587/transele.2019ECS6003},
ISSN={1745-1353},
month={December},}
Salinan
TY - JOUR
TI - Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers
T2 - IEICE TRANSACTIONS on Electronics
SP - 849
EP - 852
AU - Yongwoon SONG
AU - Dongkeon CHOI
AU - Hyukjun LEE
PY - 2019
DO - 10.1587/transele.2019ECS6003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2019
AB - The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.
ER -