The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
pandangan teks lengkap
110
Mengurangkan penggunaan kuasa adalah penting untuk peranti tepi yang menggunakan rangkaian neural convolutional (CNN). Pendekatan sifar langkau untuk CNN ialah teknik pemprosesan yang terkenal dengan penggunaan kuasa yang agak rendah dan kelajuan tinggi. Pendekatan ini menghentikan pendaraban dan pengumpulan (MAC) apabila hasil pendaraban data input dan berat adalah sifar. Walau bagaimanapun, teknik ini memerlukan litar logik yang besar dengan overhed sekitar 5%, dan kadar purata MAC berhenti adalah lebih kurang 30%. Dalam kertas ini, kami mencadangkan kaedah langkau sifar yang tepat yang menggunakan data input dan litar logik mudah untuk menghentikan pengganda dan penumpuk dengan tepat. Kami juga mencadangkan kaedah melangkau data aktif untuk mengurangkan lagi penggunaan kuasa dengan sedikit merendahkan ketepatan pengecaman. Dalam kaedah ini, setiap pengganda dan penumpuk dihentikan dengan menggunakan nilai kecil (cth, 1, 2) sebagai input. Kami melaksanakan model rangkaian pengesan berbilang kotak 500 (SSD500) pukulan tunggal pada Xilinx ZU9 dan menggunakan teknik yang dicadangkan kami. Kami mengesahkan bahawa operasi telah dihentikan pada kadar 49.1%, ketepatan pengecaman telah direndahkan sebanyak 0.29%, penggunaan kuasa dikurangkan daripada 9.2 kepada 4.4 W (-52.3%), dan overhed litar dikurangkan daripada 5.1 kepada 2.7% (-45.9% ). Teknik yang dicadangkan telah ditentukan untuk berkesan untuk mengurangkan penggunaan kuasa peranti tepi berasaskan CNN seperti FPGA.
Akira KITAYAMA
Hitachi Ltd. Research & Development Group
Goichi ONO
Hitachi Ltd. Research & Development Group
Tadashi KISHIMOTO
Hitachi Ltd. Research & Development Group
Hiroaki ITO
Hitachi Automotive Systems Ltd.
Naohiro KOHMU
Hitachi Ltd. Research & Development Group
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Salinan
Akira KITAYAMA, Goichi ONO, Tadashi KISHIMOTO, Hiroaki ITO, Naohiro KOHMU, "Low-Power Implementation Techniques for Convolutional Neural Networks Using Precise and Active Skipping Methods" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 7, pp. 330-337, July 2021, doi: 10.1587/transele.2020CDP0003.
Abstract: Reducing power consumption is crucial for edge devices using convolutional neural network (CNN). The zero-skipping approach for CNNs is a processing technique widely known for its relatively low power consumption and high speed. This approach stops multiplication and accumulation (MAC) when the multiplication results of the input data and weight are zero. However, this technique requires large logic circuits with around 5% overhead, and the average rate of MAC stopping is approximately 30%. In this paper, we propose a precise zero-skipping method that uses input data and simple logic circuits to stop multipliers and accumulators precisely. We also propose an active data-skipping method to further reduce power consumption by slightly degrading recognition accuracy. In this method, each multiplier and accumulator are stopped by using small values (e.g., 1, 2) as input. We implemented single shot multi-box detector 500 (SSD500) network model on a Xilinx ZU9 and applied our proposed techniques. We verified that operations were stopped at a rate of 49.1%, recognition accuracy was degraded by 0.29%, power consumption was reduced from 9.2 to 4.4 W (-52.3%), and circuit overhead was reduced from 5.1 to 2.7% (-45.9%). The proposed techniques were determined to be effective for lowering the power consumption of CNN-based edge devices such as FPGA.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020CDP0003/_p
Salinan
@ARTICLE{e104-c_7_330,
author={Akira KITAYAMA, Goichi ONO, Tadashi KISHIMOTO, Hiroaki ITO, Naohiro KOHMU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Implementation Techniques for Convolutional Neural Networks Using Precise and Active Skipping Methods},
year={2021},
volume={E104-C},
number={7},
pages={330-337},
abstract={Reducing power consumption is crucial for edge devices using convolutional neural network (CNN). The zero-skipping approach for CNNs is a processing technique widely known for its relatively low power consumption and high speed. This approach stops multiplication and accumulation (MAC) when the multiplication results of the input data and weight are zero. However, this technique requires large logic circuits with around 5% overhead, and the average rate of MAC stopping is approximately 30%. In this paper, we propose a precise zero-skipping method that uses input data and simple logic circuits to stop multipliers and accumulators precisely. We also propose an active data-skipping method to further reduce power consumption by slightly degrading recognition accuracy. In this method, each multiplier and accumulator are stopped by using small values (e.g., 1, 2) as input. We implemented single shot multi-box detector 500 (SSD500) network model on a Xilinx ZU9 and applied our proposed techniques. We verified that operations were stopped at a rate of 49.1%, recognition accuracy was degraded by 0.29%, power consumption was reduced from 9.2 to 4.4 W (-52.3%), and circuit overhead was reduced from 5.1 to 2.7% (-45.9%). The proposed techniques were determined to be effective for lowering the power consumption of CNN-based edge devices such as FPGA.},
keywords={},
doi={10.1587/transele.2020CDP0003},
ISSN={1745-1353},
month={July},}
Salinan
TY - JOUR
TI - Low-Power Implementation Techniques for Convolutional Neural Networks Using Precise and Active Skipping Methods
T2 - IEICE TRANSACTIONS on Electronics
SP - 330
EP - 337
AU - Akira KITAYAMA
AU - Goichi ONO
AU - Tadashi KISHIMOTO
AU - Hiroaki ITO
AU - Naohiro KOHMU
PY - 2021
DO - 10.1587/transele.2020CDP0003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2021
AB - Reducing power consumption is crucial for edge devices using convolutional neural network (CNN). The zero-skipping approach for CNNs is a processing technique widely known for its relatively low power consumption and high speed. This approach stops multiplication and accumulation (MAC) when the multiplication results of the input data and weight are zero. However, this technique requires large logic circuits with around 5% overhead, and the average rate of MAC stopping is approximately 30%. In this paper, we propose a precise zero-skipping method that uses input data and simple logic circuits to stop multipliers and accumulators precisely. We also propose an active data-skipping method to further reduce power consumption by slightly degrading recognition accuracy. In this method, each multiplier and accumulator are stopped by using small values (e.g., 1, 2) as input. We implemented single shot multi-box detector 500 (SSD500) network model on a Xilinx ZU9 and applied our proposed techniques. We verified that operations were stopped at a rate of 49.1%, recognition accuracy was degraded by 0.29%, power consumption was reduced from 9.2 to 4.4 W (-52.3%), and circuit overhead was reduced from 5.1 to 2.7% (-45.9%). The proposed techniques were determined to be effective for lowering the power consumption of CNN-based edge devices such as FPGA.
ER -