The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini mencadangkan penjana pincang badan (BBG) berasaskan kawasan dan cekap tenaga untuk operasi tenaga minimum yang mengawal pincang p-telaga dan n-telaga secara bebas. BBG boleh meminimumkan jumlah penggunaan tenaga litar sasaran di bawah keadaan proses yang condong antara nMOSFET dan pMOSFET. BBG yang dicadangkan terdiri daripada sel digital yang serasi dengan reka bentuk berasaskan sel, yang membolehkan pelaksanaan cekap tenaga dan kawasan tanpa voltan bekalan tambahan. Litar ujian dilaksanakan dalam proses FDSOI 65-nm. Keputusan pengukuran menggunakan pemproses RISC 32-bit pada cip yang sama menunjukkan bahawa BBG yang dicadangkan boleh mengurangkan penggunaan tenaga hampir kepada minimum dalam 3% kehilangan tenaga. Dalam keadaan ini, overhed tenaga dan kawasan BBG ialah 0.2% dan 0.12%, masing-masing.
Kentaro NAGAI
Kyoto University
Jun SHIOMI
Kyoto University
Hidetoshi ONODERA
Kyoto University
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Salinan
Kentaro NAGAI, Jun SHIOMI, Hidetoshi ONODERA, "A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 10, pp. 617-624, October 2021, doi: 10.1587/transele.2020CTP0002.
Abstract: This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020CTP0002/_p
Salinan
@ARTICLE{e104-c_10_617,
author={Kentaro NAGAI, Jun SHIOMI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation},
year={2021},
volume={E104-C},
number={10},
pages={617-624},
abstract={This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.},
keywords={},
doi={10.1587/transele.2020CTP0002},
ISSN={1745-1353},
month={October},}
Salinan
TY - JOUR
TI - A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 617
EP - 624
AU - Kentaro NAGAI
AU - Jun SHIOMI
AU - Hidetoshi ONODERA
PY - 2021
DO - 10.1587/transele.2020CTP0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2021
AB - This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.
ER -