The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
pandangan teks lengkap
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Secara amnya, oleh kerana hingar dalam jalur gelung terkunci fasa (PLL) disebabkan terutamanya oleh pam cas (CP), transistor bersaiz besar yang menduduki kawasan yang besar digunakan untuk menambah baik hingar dalam jalur CP. Dengan permintaan tinggi untuk hingar fasa rendah dalam sistem komunikasi berprestasi tinggi baru-baru ini, isu pertukaran antara kawasan yang diduduki dan hingar dalam CP konvensional telah menjadi ketara. Litar CP yang membatalkan hingar dibentangkan dalam kertas ini untuk mengurangkan pertukaran antara kawasan yang diduduki dan hingar. CP yang dicadangkan boleh mencapai prestasi hingar yang lebih rendah daripada CP konvensional dengan melakukan pembatalan hingar tambahan. Mengikut keputusan simulasi, CP yang dicadangkan boleh mengurangkan hingar semasa kepada 57% dengan kawasan yang diduduki yang sama, atau boleh mengurangkan kawasan yang diduduki kepada 22% berbanding dengan CP konvensional pada prestasi hingar yang sama. Kami mencipta prototaip CP yang dicadangkan yang dibenamkan dalam LC-PLL 28-GHz menggunakan proses FinFET 16-nm, dan peningkatan 1.2-dB dalam hingar fasa bersepadu jalur sisi tunggal dicapai.
Go URAKAWA
Kioxia Corporation
Hiroyuki KOBAYASHI
Kioxia Corporation
Jun DEGUCHI
Kioxia Corporation
Ryuichi FUJIMOTO
Kioxia Corporation
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Salinan
Go URAKAWA, Hiroyuki KOBAYASHI, Jun DEGUCHI, Ryuichi FUJIMOTO, "A Noise-Canceling Charge Pump for Area Efficient PLL Design" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 10, pp. 625-634, October 2021, doi: 10.1587/transele.2020CTP0004.
Abstract: In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020CTP0004/_p
Salinan
@ARTICLE{e104-c_10_625,
author={Go URAKAWA, Hiroyuki KOBAYASHI, Jun DEGUCHI, Ryuichi FUJIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Noise-Canceling Charge Pump for Area Efficient PLL Design},
year={2021},
volume={E104-C},
number={10},
pages={625-634},
abstract={In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.},
keywords={},
doi={10.1587/transele.2020CTP0004},
ISSN={1745-1353},
month={October},}
Salinan
TY - JOUR
TI - A Noise-Canceling Charge Pump for Area Efficient PLL Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 625
EP - 634
AU - Go URAKAWA
AU - Hiroyuki KOBAYASHI
AU - Jun DEGUCHI
AU - Ryuichi FUJIMOTO
PY - 2021
DO - 10.1587/transele.2020CTP0004
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2021
AB - In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.
ER -