The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Peranti IoT terkini memerlukan penggunaan kuasa siap sedia yang sangat rendah, manakala prestasi tertentu diperlukan semasa masa aktif, dan Tatasusunan Boleh Dikonfigurasi Semula Berbutir Kasar (CGRA) telah mendapat perhatian kerana kecekapan tenaganya yang tinggi. Untuk pengurangan selanjutnya penggunaan tenaga siap sedia CGRA, kuasa kebocoran untuk memori konfigurasinya mesti dikurangkan. Walaupun power gating adalah teknik biasa, data yang hilang dalam flip-flop dan ingatan mesti diambil selepas bangun. Memulihkan segala-galanya memerlukan banyak peralihan keadaan dan overhed yang besar pada masa dan tenaga pelaksanaannya. Untuk menangani masalah tersebut, Non-volatile Cool Mega Array (NVCMA), sebuah CGRA yang menyediakan flip-flop tidak meruap (NVFF) dengan teknologi memori tidak meruap jenis tork pemindahan putaran (NVM) telah dibangunkan. Walau bagaimanapun, secara amnya, teknologi memori tidak meruap mempunyai masalah dengan kebolehpercayaan. Sesetengah NVFF disusun pada-0/1, dan tidak boleh menyimpan data dalam kemungkinan tertentu. Untuk meningkatkan hasil cip, kami mencadangkan algoritma pemetaan untuk mengelakkan elemen pemprosesan yang rosak CGRA yang disebabkan oleh data konfigurasi yang salah. Seterusnya, kami juga mencadangkan kaedah untuk menambah mekanisme kod pembetulan ralat (ECC) pada NVFF untuk konfigurasi dan ingatan malar. Kaedah yang dicadangkan telah digunakan untuk NVCMA untuk menilai kadar ketersediaan dan pengurangan masa menulis. Dengan menggunakan kedua-dua kaedah, nisbah ketersediaan purata sebanyak 94.2% telah dicapai, manakala nisbah ketersediaan purata bagi sembilan aplikasi ialah 0.056% apabila kebarangkalian kegagalan FF ialah 0.01. Tenaga untuk menyimpan data menjadi kira-kira 2.3 kali ganda kerana overhed perkakasan ECC tetapi kaedah yang dicadangkan boleh menjimatkan 8.6% kuasa penulisan secara purata.
Takeharu IKEZOE
Keio University
Takuya KOJIMA
Keio University
Hideharu AMANO
Keio University
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Salinan
Takeharu IKEZOE, Takuya KOJIMA, Hideharu AMANO, "Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 6, pp. 215-225, June 2021, doi: 10.1587/transele.2020LHP0002.
Abstract: Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse-Grained Reconfigurable Arrays (CGRAs) have received attention because of their high energy efficiency. For further reduction of the standby energy consumption of CGRAs, the leakage power for their configuration memory must be reduced. Although the power gating is a common technique, the lost data in flip-flops and memory must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Next, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the average availability ratio of 94.2% was achieved, while the average availability ratio of the nine applications was 0.056% when the probability of failure of the FF was 0.01. The energy for storing data becomes about 2.3 times because of the hardware overhead of ECC but the proposed method can save 8.6% of the writing power on average.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020LHP0002/_p
Salinan
@ARTICLE{e104-c_6_215,
author={Takeharu IKEZOE, Takuya KOJIMA, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures},
year={2021},
volume={E104-C},
number={6},
pages={215-225},
abstract={Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse-Grained Reconfigurable Arrays (CGRAs) have received attention because of their high energy efficiency. For further reduction of the standby energy consumption of CGRAs, the leakage power for their configuration memory must be reduced. Although the power gating is a common technique, the lost data in flip-flops and memory must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Next, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the average availability ratio of 94.2% was achieved, while the average availability ratio of the nine applications was 0.056% when the probability of failure of the FF was 0.01. The energy for storing data becomes about 2.3 times because of the hardware overhead of ECC but the proposed method can save 8.6% of the writing power on average.},
keywords={},
doi={10.1587/transele.2020LHP0002},
ISSN={1745-1353},
month={June},}
Salinan
TY - JOUR
TI - Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures
T2 - IEICE TRANSACTIONS on Electronics
SP - 215
EP - 225
AU - Takeharu IKEZOE
AU - Takuya KOJIMA
AU - Hideharu AMANO
PY - 2021
DO - 10.1587/transele.2020LHP0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2021
AB - Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse-Grained Reconfigurable Arrays (CGRAs) have received attention because of their high energy efficiency. For further reduction of the standby energy consumption of CGRAs, the leakage power for their configuration memory must be reduced. Although the power gating is a common technique, the lost data in flip-flops and memory must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Next, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the average availability ratio of 94.2% was achieved, while the average availability ratio of the nine applications was 0.056% when the probability of failure of the FF was 0.01. The energy for storing data becomes about 2.3 times because of the hardware overhead of ECC but the proposed method can save 8.6% of the writing power on average.
ER -