The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan pencirian pada cip bagi impak nyahcas elektrostatik (ESD) yang digunakan pada bahagian belakang Si-substrat cip litar bersepadu (FC-IC) dipasang cip flip. Cip FC-IC mempunyai bahagian belakang terbuka dan terdapat ancaman masalah kebolehpercayaan dan kerosakan yang disebabkan oleh bahagian belakang ESD. Kami menyediakan cip FC-IC ujian dan mengukur turun naik voltan Si-substrat di bahagian hadapannya dengan litar monitor on-chip (OCM). Lonjakan voltan setinggi 200mV diperhatikan pada bahagian hadapan apabila pistol ESD 200-V disinari melalui perintang sentuhan 5kΩ di bahagian belakang substrat Si setebal 350μm. Taburan ketinggian voltan diukur secara eksperimen di 20 lokasi pada cip di antara substrat Si yang dinipiskan sehingga 40μm, dan juga dijelaskan dalam simulasi tahap sistem penuh kesan ESD bahagian belakang dengan model setara bagi operasi pistol ESD dan pemasangan cip FC-IC .
Takuya WADATSUMI
Kobe University
Kohei KAWAI
Kobe University
Rikuu HASEGAWA
Kobe University
Kikuo MURAMATSU
e-SYNC Co., Ltd.
Hiromu HASEGAWA
MegaChips Corp.
Takuya SAWADA
MegaChips Corp.
Takahito FUKUSHIMA
MegaChips Corp.
Hisashi KONDO
MegaChips Corp.
Takuji MIKI
Kobe University
Makoto NAGATA
Kobe University
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Salinan
Takuya WADATSUMI, Kohei KAWAI, Rikuu HASEGAWA, Kikuo MURAMATSU, Hiromu HASEGAWA, Takuya SAWADA, Takahito FUKUSHIMA, Hisashi KONDO, Takuji MIKI, Makoto NAGATA, "Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 556-564, October 2023, doi: 10.1587/transele.2022CTP0004.
Abstract: This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTP0004/_p
Salinan
@ARTICLE{e106-c_10_556,
author={Takuya WADATSUMI, Kohei KAWAI, Rikuu HASEGAWA, Kikuo MURAMATSU, Hiromu HASEGAWA, Takuya SAWADA, Takahito FUKUSHIMA, Hisashi KONDO, Takuji MIKI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging},
year={2023},
volume={E106-C},
number={10},
pages={556-564},
abstract={This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.},
keywords={},
doi={10.1587/transele.2022CTP0004},
ISSN={1745-1353},
month={October},}
Salinan
TY - JOUR
TI - Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging
T2 - IEICE TRANSACTIONS on Electronics
SP - 556
EP - 564
AU - Takuya WADATSUMI
AU - Kohei KAWAI
AU - Rikuu HASEGAWA
AU - Kikuo MURAMATSU
AU - Hiromu HASEGAWA
AU - Takuya SAWADA
AU - Takahito FUKUSHIMA
AU - Hisashi KONDO
AU - Takuji MIKI
AU - Makoto NAGATA
PY - 2023
DO - 10.1587/transele.2022CTP0004
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.
ER -