The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kerumitan dan skala Networks-on-Chip (NoCs) semakin berkembang apabila lebih banyak elemen pemprosesan dan peranti memori dilaksanakan pada cip. Walau bagaimanapun, di bawah belanjawan kuasa yang ketat, adalah penting untuk mengurangkan penggunaan kuasa NoC demi kecekapan tenaga. Dalam makalah ini, kami membentangkan tiga reka bentuk unit input baru untuk penghala pada cip yang cuba mengecilkan penggunaan kuasa mereka sambil masih mengekalkan prestasi rangkaian. Idea utama di sebalik reka bentuk kami adalah untuk mengatur penimbal dalam unit input dengan mengambil kira ciri trafik rangkaian; seperti dalam pemerhatian kami, hanya sebahagian kecil trafik rangkaian adalah paket panjang (terdiri daripada berbilang flits), yang bermaksud, adalah adil untuk melaksanakan penimbal hibrid, tidak simetri dan boleh dikonfigurasikan semula supaya ia menyasarkan terutamanya pada paket pendek (hanya mempunyai flit tunggal), maka penggunaan kuasa dan kawasan overhed yang lebih kecil. Penilaian menunjukkan bahawa reka bentuk unit input hibrid, asimetri dan boleh dikonfigurasikan semula kami boleh mencapai pengurangan purata penggunaan tenaga setiap flit sebanyak 45%, 52.3% dan 56.2% di bawah 93.6% (untuk reka bentuk hibrid) dan 66.3% (untuk reka bentuk asimetri dan boleh dikonfigurasikan semula) daripada kawasan penghala asal, masing-masing. Sementara itu, kami hanya melihat kemerosotan kecil dalam kependaman rangkaian (antara 18.4% hingga 1.5%, secara purata) dengan cadangan kami.
Xiaoman LIU
Shenyang University of Technology
Yujie GAO
Shenyang University of Technology
Yuan HE
Shenyang University of Technology,Keio University
Xiaohan YUE
Shenyang University of Technology
Haiyan JIANG
Shenyang University of Technology
Xibo WANG
Shenyang University of Technology
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Salinan
Xiaoman LIU, Yujie GAO, Yuan HE, Xiaohan YUE, Haiyan JIANG, Xibo WANG, "Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 570-579, October 2023, doi: 10.1587/transele.2022CTP0005.
Abstract: The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTP0005/_p
Salinan
@ARTICLE{e106-c_10_570,
author={Xiaoman LIU, Yujie GAO, Yuan HE, Xiaohan YUE, Haiyan JIANG, Xibo WANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks},
year={2023},
volume={E106-C},
number={10},
pages={570-579},
abstract={The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.},
keywords={},
doi={10.1587/transele.2022CTP0005},
ISSN={1745-1353},
month={October},}
Salinan
TY - JOUR
TI - Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks
T2 - IEICE TRANSACTIONS on Electronics
SP - 570
EP - 579
AU - Xiaoman LIU
AU - Yujie GAO
AU - Yuan HE
AU - Xiaohan YUE
AU - Haiyan JIANG
AU - Xibo WANG
PY - 2023
DO - 10.1587/transele.2022CTP0005
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.
ER -