The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Ringkas ini mempersembahkan teknik serangan saluran sisi (SCA) pada penukar analog-ke-digital (ADC) daftar penghampiran berturut-turut tak segerak (SAR) berkelajuan tinggi. Rangkaian neural dwi yang dicadangkan berdasarkan pelbagai bentuk gelombang hingar secara berasingan mendedahkan maklumat tanda dan nilai mutlak isyarat input yang disembunyikan oleh struktur pembezaan dan operasi tak segerak berkelajuan tinggi. Sasaran SAR ADC dan pemantau hingar pada cip direka pada cip prototaip tunggal untuk demonstrasi SCA. Dicipta dalam 40 nm, keputusan eksperimen menunjukkan serangan yang dicadangkan pada SAR ADC tak segerak berjaya memulihkan data input dengan ketepatan kompetitif dalam ralat 300 mV rms.
Ryozo TAKAHASHI
Kobe University
Takuji MIKI
Kobe University
Makoto NAGATA
Kobe University
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Salinan
Ryozo TAKAHASHI, Takuji MIKI, Makoto NAGATA, "An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 565-569, October 2023, doi: 10.1587/transele.2022CTS0002.
Abstract: This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300 mV rms error.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTS0002/_p
Salinan
@ARTICLE{e106-c_10_565,
author={Ryozo TAKAHASHI, Takuji MIKI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique},
year={2023},
volume={E106-C},
number={10},
pages={565-569},
abstract={This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300 mV rms error.},
keywords={},
doi={10.1587/transele.2022CTS0002},
ISSN={1745-1353},
month={October},}
Salinan
TY - JOUR
TI - An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 565
EP - 569
AU - Ryozo TAKAHASHI
AU - Takuji MIKI
AU - Makoto NAGATA
PY - 2023
DO - 10.1587/transele.2022CTS0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300 mV rms error.
ER -