The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan teknik penentukuran modulasi digital sepenuhnya untuk ketidakpadanan saluran TIADC pada sebarang frekuensi. Dengan pra-masukan isyarat ujian dalam TIADC, ralat ketidakpadanan dianggarkan dan disimpan, dan nilai yang disimpan akan diekstrak untuk pampasan apabila isyarat input berada pada frekuensi khas yang boleh dikesan oleh modul penghakiman ambang, sekali gus menyelesaikan masalah yang algoritma penentukuran modulasi tradisional tidak boleh menentukur isyarat pada frekuensi khas. Kemudian, dengan melaraskan susunan operasi antara pekali anggaran ralat, fungsi modulasi dan isyarat input dalam gelung penentukuran, seterusnya, susunan korelasi dan modulasi dalam modul anggaran ralat, kerumitan algoritma penentukuran yang dicadangkan akan dikurangkan dengan ketara dan ia akan tidak bertambah dengan bilangan saluran TIADC. Lebih-lebih lagi, penggunaan perkakasan penapis dalam algoritma penentukuran dikurangkan dengan banyaknya dengan memperkenalkan teknik pengekodan CSD (Canonical Signed Digit) berdasarkan peraturan Horner dan perkongsian sub-ungkapan. Digunakan pada sistem TIADC 14bit 560MHz empat saluran, dengan isyarat input pada 75.6MHz, keputusan pengesahan FPGA menunjukkan bahawa, selepas penentukuran, julat dinamik bebas palsu (SFDR) bertambah baik daripada 33.47dB kepada 99.81dB dan isyarat-ke-bunyi nisbah herotan (SNDR) meningkat daripada 30.15dB kepada 81.89dB.
Hongmei CHEN
Hefei University of Technology
Jian WANG
Hefei University of Technology
Lanyu WANG
Hefei University of Technology
Long LI
Hefei University of Technology
Honghui DENG
Hefei University of Technology
Xu MENG
Hefei University of Technology
Yongsheng YIN
Hefei University of Technology
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Salinan
Hongmei CHEN, Jian WANG, Lanyu WANG, Long LI, Honghui DENG, Xu MENG, Yongsheng YIN, "Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 3, pp. 84-92, March 2023, doi: 10.1587/transele.2022ECP5023.
Abstract: This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022ECP5023/_p
Salinan
@ARTICLE{e106-c_3_84,
author={Hongmei CHEN, Jian WANG, Lanyu WANG, Long LI, Honghui DENG, Xu MENG, Yongsheng YIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency},
year={2023},
volume={E106-C},
number={3},
pages={84-92},
abstract={This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.},
keywords={},
doi={10.1587/transele.2022ECP5023},
ISSN={1745-1353},
month={March},}
Salinan
TY - JOUR
TI - Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency
T2 - IEICE TRANSACTIONS on Electronics
SP - 84
EP - 92
AU - Hongmei CHEN
AU - Jian WANG
AU - Lanyu WANG
AU - Long LI
AU - Honghui DENG
AU - Xu MENG
AU - Yongsheng YIN
PY - 2023
DO - 10.1587/transele.2022ECP5023
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2023
AB - This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.
ER -