The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam penyelidikan ini, kami menyiasat voltan ambang (VTH) kawalan melalui polarisasi separa transistor kesan medan-ferroelektrik-semikonduktor logam (MFSFET) dengan HfO tak berdop setebal 5 nm2 penebat pintu menggunakan percikan Kr-plasma untuk pemendapan elektrod pintu Pt. Polarisasi sisa (2Pr) sebanyak 7.2 μC/cm2 telah direalisasikan oleh Kr-plasma sputtering untuk pemendapan elektrod pintu Pt. Tetingkap ingatan (MW) 0.58 V direalisasikan oleh amplitud nadi dan lebar -5/5 V, 100 ms. Tambahan pula, VTH MFSFET boleh dikawal oleh nadi input program/padam (P/E) walaupun dengan lebar nadi di bawah 100 ns yang mungkin disebabkan oleh pengurangan arus bocor dengan kerosakan plasma yang berkurangan.
Joong-Won SHIN
Tokyo Institute of Technology
Masakazu TANUMA
Tokyo Institute of Technology
Shun-ichiro OHMI
Tokyo Institute of Technology
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Salinan
Joong-Won SHIN, Masakazu TANUMA, Shun-ichiro OHMI, "Kr-Plasma Sputtering for Pt Gate Electrode Deposition on MFSFET with 5 nm-Thick Ferroelectric Nondoped HfO2 Gate Insulator for Analog Memory Application" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 581-587, October 2023, doi: 10.1587/transele.2022FUP0003.
Abstract: In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022FUP0003/_p
Salinan
@ARTICLE{e106-c_10_581,
author={Joong-Won SHIN, Masakazu TANUMA, Shun-ichiro OHMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Kr-Plasma Sputtering for Pt Gate Electrode Deposition on MFSFET with 5 nm-Thick Ferroelectric Nondoped HfO2 Gate Insulator for Analog Memory Application},
year={2023},
volume={E106-C},
number={10},
pages={581-587},
abstract={In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.},
keywords={},
doi={10.1587/transele.2022FUP0003},
ISSN={1745-1353},
month={October},}
Salinan
TY - JOUR
TI - Kr-Plasma Sputtering for Pt Gate Electrode Deposition on MFSFET with 5 nm-Thick Ferroelectric Nondoped HfO2 Gate Insulator for Analog Memory Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 581
EP - 587
AU - Joong-Won SHIN
AU - Masakazu TANUMA
AU - Shun-ichiro OHMI
PY - 2023
DO - 10.1587/transele.2022FUP0003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.
ER -