The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini menerangkan seni bina dan pelaksanaan litar penalaan digital automatik untuk penapis laluan jalur kompleks (BPF) dalam transceiver berkuasa rendah dan kos rendah untuk aplikasi seperti pengesahan peribadi dan sistem rangkaian penderia wayarles. Analisis reka bentuk seni bina menunjukkan bahawa penapis RC aktif dalam seni bina JIKA rendah boleh sekurang-kurangnya 47.7% lebih kecil dalam kawasan daripada g konvensionalm-C penapis; di samping itu, ia menampilkan pelaksanaan mudah litar penalaan yang berkaitan. Prinsip penalaan serentak kedua-dua frekuensi tengah dan lebar jalur melalui penentukuran tatasusunan kapasitor digambarkan sebagai berdasarkan analisis ciri penapis, dan litar penalaan digital automatik berskala dengan blok analog mudah dan logik kawalan yang mempunyai hanya 835 get diperkenalkan. Teknik penalaan kapasitor yang dibangunkan boleh mencapai ralat penalaan kurang daripada
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Salinan
Hideaki KONDO, Masaru SAWADA, Norio MURAKAMI, Shoichi MASUI, "Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1304-1310, October 2009, doi: 10.1587/transele.E92.C.1304.
Abstract: This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1304/_p
Salinan
@ARTICLE{e92-c_10_1304,
author={Hideaki KONDO, Masaru SAWADA, Norio MURAKAMI, Shoichi MASUI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers},
year={2009},
volume={E92-C},
number={10},
pages={1304-1310},
abstract={This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than
keywords={},
doi={10.1587/transele.E92.C.1304},
ISSN={1745-1353},
month={October},}
Salinan
TY - JOUR
TI - Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers
T2 - IEICE TRANSACTIONS on Electronics
SP - 1304
EP - 1310
AU - Hideaki KONDO
AU - Masaru SAWADA
AU - Norio MURAKAMI
AU - Shoichi MASUI
PY - 2009
DO - 10.1587/transele.E92.C.1304
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than
ER -