The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini mencadangkan seni bina cache saiz talian pembolehubah boleh dikawal perisian (SC-VLS) untuk sistem terbenam kuasa rendah. Jalur lebar tinggi antara logik dan DRAM direalisasikan melalui teknologi bersepadu termaju. System-in-Silicon ialah salah satu rangka kerja seni bina untuk merealisasikan lebar jalur yang tinggi. ASIC dan SRAM tertentu dipasang pada interposer silikon. Setiap cip disambungkan kepada interposer silikon oleh benjolan pateri eutektik. Dalam rangka kerja, adalah penting untuk mengurangkan penggunaan tenaga DRAM. DRAM khusus memerlukan memori cache yang kecil untuk meningkatkan prestasi. Kami mengeksploitasi cache untuk mengurangkan penggunaan tenaga DRAM. Semasa pelaksanaan program aplikasi, saiz baris cache yang mencukupi yang menghasilkan nisbah kehilangan cache terendah adalah berbeza-beza kerana jumlah lokaliti ruang rujukan memori berubah. Jika kami menggunakan saiz baris cache yang besar, kami boleh menjangkakan kesan prapengambilan. Walau bagaimanapun, penggunaan tenaga DRAM lebih besar daripada saiz talian yang kecil kerana bilangan bank yang banyak diakses. Cache SC-VLS dapat menukar saiz talian kepada saiz yang mencukupi pada masa jalan dengan kawasan kecil dan overhed kuasa. Kami menganalisis saiz baris yang mencukupi dan memasukkan arahan perubahan saiz baris pada permulaan setiap fungsi program sasaran sebelum melaksanakan program. Dalam penilaian kami, diperhatikan bahawa cache SC-VLS mengurangkan penggunaan tenaga DRAM sehingga 88%, berbanding cache konvensional dengan talian 256 B tetap.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Takatsugu ONO, Koji INOUE, Kazuaki MURAKAMI, Kenji YOSHIDA, "Reducing On-Chip DRAM Energy via Data Transfer Size Optimization" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 433-443, April 2009, doi: 10.1587/transele.E92.C.433.
Abstract: This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.433/_p
Salinan
@ARTICLE{e92-c_4_433,
author={Takatsugu ONO, Koji INOUE, Kazuaki MURAKAMI, Kenji YOSHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Reducing On-Chip DRAM Energy via Data Transfer Size Optimization},
year={2009},
volume={E92-C},
number={4},
pages={433-443},
abstract={This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.},
keywords={},
doi={10.1587/transele.E92.C.433},
ISSN={1745-1353},
month={April},}
Salinan
TY - JOUR
TI - Reducing On-Chip DRAM Energy via Data Transfer Size Optimization
T2 - IEICE TRANSACTIONS on Electronics
SP - 433
EP - 443
AU - Takatsugu ONO
AU - Koji INOUE
AU - Kazuaki MURAKAMI
AU - Kenji YOSHIDA
PY - 2009
DO - 10.1587/transele.E92.C.433
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.
ER -