The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini menerangkan pemodelan dan metodologi analisis untuk menilai Bunyi Pensuisan Serentak (SSN) untuk sistem gabungan pakej dengan Papan Litar Bercetak (PCB) 4 lapisan, yang mana 64 Output Pensuisan Serentak (SSO) telah disertakan menggunakan model IBIS. Keputusan simulasi menunjukkan bahawa satah tanah dalam kedua-dua pakej dan PCB boleh digunakan sebagai rujukan untuk mengurangkan SSN dengan lebih berkesan daripada satah kuasa. Untuk teknik pemasaan segerak sumber seperti yang digunakan dalam bas memori DDR SDRAM dalam model yang ditunjukkan dalam kertas ini, tequiniqe litar kawalan condong mudah digunakan dalam reka bentuk cip dan bukannya menggunakan kapasitor terbenam dalam substrat pakej. Dan juga analisis pancaran dan gambar rajah mata telah dikaji.
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Salinan
Narimasa TAKAHASHI, Kenji KAGAWA, Yutaka HONDA, Yo TAKAHASHI, "Simultaneous Switching Noise Analysis for High-Speed Interface" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 460-467, April 2009, doi: 10.1587/transele.E92.C.460.
Abstract: This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.460/_p
Salinan
@ARTICLE{e92-c_4_460,
author={Narimasa TAKAHASHI, Kenji KAGAWA, Yutaka HONDA, Yo TAKAHASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Simultaneous Switching Noise Analysis for High-Speed Interface},
year={2009},
volume={E92-C},
number={4},
pages={460-467},
abstract={This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.},
keywords={},
doi={10.1587/transele.E92.C.460},
ISSN={1745-1353},
month={April},}
Salinan
TY - JOUR
TI - Simultaneous Switching Noise Analysis for High-Speed Interface
T2 - IEICE TRANSACTIONS on Electronics
SP - 460
EP - 467
AU - Narimasa TAKAHASHI
AU - Kenji KAGAWA
AU - Yutaka HONDA
AU - Yo TAKAHASHI
PY - 2009
DO - 10.1587/transele.E92.C.460
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.
ER -