The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pembatal hingar bekalan kuasa pada cip dengan bekalan voltan yang lebih tinggi dan transistor pensuisan dicadangkan dan keberkesanan pembatalan itu disahkan secara eksperimen. Pembatal hingar berkesan untuk bunyi tertib nano detik yang disebabkan oleh bangun litar atau peningkatan langkah kekerapan dalam lompat frekuensi. Prinsip pembatalan hingar adalah untuk mengurangkan arus yang mengalir melalui talian bekalan VDD dengan menyuntik arus tambahan daripada bekalan voltan yang lebih tinggi, supaya voltan jatuh merentasi VDD talian bekalan dikurangkan. Sebagai aliran arus tambahan daripada bekalan yang lebih tinggi, transistor pensuisan perlu dimatikan untuk tidak meningkatkan penggunaan kuasa. Dengan masa tutup 2L/R, arus ini boleh dimatikan tanpa mengaruhkan droop lain disebabkan peningkatan arus yang mengalir melalui talian bekalan kuasa. Pengukuran menunjukkan pembatal mengurangkan 68% daripada hingar dengan litar beban bersamaan dengan 530 k get logik dalam 90-nm CMOS dengan 9% overhed wayar, 1.5% overhed kawasan dan 3% overhed kuasa pada 50 k bangun/s. Berbanding dengan pengurangan hingar pasif, pembatalan hingar yang dicadangkan mengurangkan hingar bekalan kuasa sebanyak 64% tanpa overhed wayar dan untuk mencapai pengurangan hingar yang sama dengan kaedah pasif, 77 kali lebih banyak. C atau kurang 45 kali ganda L adalah diperlukan. Transistor pensuisan yang terlalu besar mengakibatkan kesan pengurangan hingar tepu dan penggunaan kuasa yang lebih tinggi. Peraturan-peraturan adalah untuk menetapkan rintangan-hidup untuk membekalkan 100% arus beban apabila dihidupkan.
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Salinan
Yasumi NAKAMURA, Makoto TAKAMIYA, Takayasu SAKURAI, "An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 468-474, April 2009, doi: 10.1587/transele.E92.C.468.
Abstract: An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.468/_p
Salinan
@ARTICLE{e92-c_4_468,
author={Yasumi NAKAMURA, Makoto TAKAMIYA, Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise},
year={2009},
volume={E92-C},
number={4},
pages={468-474},
abstract={An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.},
keywords={},
doi={10.1587/transele.E92.C.468},
ISSN={1745-1353},
month={April},}
Salinan
TY - JOUR
TI - An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
T2 - IEICE TRANSACTIONS on Electronics
SP - 468
EP - 474
AU - Yasumi NAKAMURA
AU - Makoto TAKAMIYA
AU - Takayasu SAKURAI
PY - 2009
DO - 10.1587/transele.E92.C.468
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.
ER -