The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Sistem LSI berkelajuan tinggi dan berkuasa rendah dalam beberapa tahun kebelakangan ini mempunyai keperluan penting untuk mengurus bunyi bekalan kuasa supaya ia mungkin tidak menjejaskan fungsi dan prestasi litar dengan ketara. Kapasiti penyahgandingan dikenali sebagai langkah berkesan untuk menyekat hingar bekalan kuasa. Dalam makalah ini, kami mencadangkan metodologi reka bentuk untuk belanjawan kapasitans nyah gandingan, di mana kapasitans penyahgandingan diagihkan dengan sewajarnya ke atas kawasan cip LSI untuk menyekat hingar bekalan kuasa setiap wilayah tempatan. Untuk belanjawan yang cekap, kami memperkenalkan konsep baharu nisbah kuasa-kapasiti, iaitu nisbah pelesapan kuasa kepada kemuatan. Kaedah yang dicadangkan mula-mula melakukan analisis hingar bekalan kuasa yang dipermudahkan dengan menggunakan model litar terkumpul untuk menentukan jumlah kapasitans pada cip yang diperlukan, dan mengira nisbah kapasitans kuasa. Kemudian, dalam fasa reka bentuk susun atur, belanjawan kemuatan penyahgandingan dilakukan dengan menggunakan nisbah kapasitans kuasa di atas sebagai garis panduan. Keberkesanan kaedah yang dicadangkan telah disahkan dengan menggunakan simulasi SPICE pada contoh model cip nod teknologi 90 nm. Keputusan pengesahan menunjukkan bahawa, walaupun untuk cip dengan variasi pada cip yang sangat luas dalam ketumpatan kuasa, kaedah yang dicadangkan boleh menyekat hingar bekalan kuasa setiap wilayah setempat dengan berkesan.
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Salinan
Susumu KOBAYASHI, Naoshi DOI, "An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 492-499, April 2009, doi: 10.1587/transele.E92.C.492.
Abstract: The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90 nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.492/_p
Salinan
@ARTICLE{e92-c_4_492,
author={Susumu KOBAYASHI, Naoshi DOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio},
year={2009},
volume={E92-C},
number={4},
pages={492-499},
abstract={The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90 nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively.},
keywords={},
doi={10.1587/transele.E92.C.492},
ISSN={1745-1353},
month={April},}
Salinan
TY - JOUR
TI - An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio
T2 - IEICE TRANSACTIONS on Electronics
SP - 492
EP - 499
AU - Susumu KOBAYASHI
AU - Naoshi DOI
PY - 2009
DO - 10.1587/transele.E92.C.492
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90 nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively.
ER -