The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Surat ini membentangkan penjana jam ultra rendah jitter yang menggunakan LC-VCO yang cekap kawasan. Untuk menggunakan sepenuhnya kawasan induktor pada cip, penapis gelung gelung berkunci fasa (PLL) terletak di bawah induktor. Cip prototaip yang dilaksanakan dalam proses CMOS 0.13 µm mencapai 105 MHz hingga 225 MHz frekuensi jam sambil menggunakan 4.2 mW daripada bekalan 1.2 V. Jitter rms yang diukur dan jitter rms ternormal bagi penjana jam yang dicadangkan ialah 2.8 ps dan 0.031% pada 105 MHz, masing-masing.
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Salinan
Joonhee LEE, Sungjun KIM, Sehyung JEON, Woojae LEE, SeongHwan CHO, "A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 589-591, April 2009, doi: 10.1587/transele.E92.C.589.
Abstract: This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.589/_p
Salinan
@ARTICLE{e92-c_4_589,
author={Joonhee LEE, Sungjun KIM, Sehyung JEON, Woojae LEE, SeongHwan CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS},
year={2009},
volume={E92-C},
number={4},
pages={589-591},
abstract={This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.},
keywords={},
doi={10.1587/transele.E92.C.589},
ISSN={1745-1353},
month={April},}
Salinan
TY - JOUR
TI - A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 589
EP - 591
AU - Joonhee LEE
AU - Sungjun KIM
AU - Sehyung JEON
AU - Woojae LEE
AU - SeongHwan CHO
PY - 2009
DO - 10.1587/transele.E92.C.589
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.
ER -